Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. G | Page 98 of 108
Table 96. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
Setting
Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x10 WLCSP required.
0x01 0x00 SD input mode.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xD3 Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
0x8C 0x0C Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
0x8D 0x8C
0x8E 0x79
0x8F 0x26
Table 97. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xD3 Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
0x87 0x80 RGB input enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
0x8C 0x0C Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
0x8D 0x8C
0x8E
0x79
0x8F 0x26