Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 99 of 108
ENHANCED DEFINITION
Table 98. ED Configuration Scripts
Input Format Input Data Width Synchronization Format Input Color Space Output Color Space Table Number
525p
8-bit DDR
EAV/SAV
YCrCb
YPrPb
Table 107
525p 8-bit DDR EAV/SAV YCrCb RGB Table 109
525p 10-bit DDR EAV/SAV YCrCb YPrPb Table 108
525p 10-bit DDR EAV/SAV YCrCb RGB Table 110
525p 16-bit SDR EAV/SAV YCrCb YPrPb Table 99
525p 16-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 100
525p 16-bit SDR EAV/SAV YCrCb RGB Table 101
525p 16-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 102
625p
8-bit DDR
EAV/SAV
YCrCb
YPrPb
Table 111
625p 8-bit DDR EAV/SAV YCrCb RGB Table 113
625p 10-bit DDR EAV/SAV YCrCb YPrPb Table 112
625p 10-bit DDR EAV/SAV YCrCb RGB Table 114
625p 16-bit SDR EAV/SAV YCrCb YPrPb Table 103
625p 16-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 104
625p 16-bit SDR EAV/SAV YCrCb RGB Table 105
625p 16-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 106
Table 99. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x04 525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 100. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x00 525p at 59.94 Hz.
HSYNC
/
VSYNC
synch-
ronization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 101. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x04 525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 102. 16-Bit 525p YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x30 0x00 525p at 59.94 Hz.
HSYNC
/
VSYNC
synch-
ronization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 103. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x30 0x1C 625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 104. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress
Setting
Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x18 625p at 50 Hz.
HSYNC
/
VSYNC
synch-
ronization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.