Datasheet

ADSP-21262 EZ-KIT Lite Evaluation System Manual 2-3
ADSP-21262 EZ-KIT Lite Hardware Reference
sor. The
R79 resistor provides access to the IO voltage of the processor,
and the R80 resistor provides access to the core voltage plane of the
processor.
The CLKIN pin of the processor connects to a 25 MHz oscillator. The core
frequency of the processor is derived by multiplying the frequency at the
CLKIN pin by a value determined by the state of the processor pins,
CLKCFG1 and CLKCFG0. The value at these pins is determined by the state of
the SW10 switch (see “Boot Mode and Clock Ratio Select Switch (SW10)”
on page 2-12). By default, the EZ-KIT Lite gives a core frequency of
200 MHz.
The SW10 switch also configures the boot mode of the processor. The
EZ-KIT Lite is capable of parallel port boot and serial port interconnect
(SPI) master boot. By default, the EZ-KIT Lite boots from the parallel
port. For information about configuring the boot modes, see “Boot Mode
and Clock Ratio Select Switch (SW10)” on page 2-12.
Parallel Port
The parallel port (PP) of the ADSP-21262 processor consists of a 16-bit
multiplex address/data memory bus (AD15–0) and an address latch-enable
pin (ALE). The interface does not have any memory select pins; these sig-
nals must be generated by decoding the address.
The PP connections to the EZ-KIT Lite are shown in Figure 2-2. The PP
connects to an 8-bit parallel flash memory, an 8-bit SRAM memory, and
eight general-purpose LEDs. The upper three address bits connect to a
3-to-8 decoder, providing eight memory select pins. See “External Mem-
ory” on page 1-7 for more information about accessing the flash and
SDRAM memories.