Datasheet

System Architecture
2-6 ADSP-21262 EZ-KIT Lite Evaluation System Manual
To use the DAI for a different purpose, disable any signal, which is driv-
ing the DAI pins, with a switch. See “Codec Setup Switch (SW7)” on
page 2-10 and “S/PDIF Signal Enable Switch (SW8)” on page 2-11 for
how to information. In addition, the codec setup switch allows flexible
routing of the 12.288 MHz audio oscillator’s output signal. By default,
this signal is used as the master clock (
MCLK) for the AD1835A codec.
SPI Interface
The processor’s serial peripheral interconnect (SPI) interface connects to
an SPI flash memory, the CS8416 S/PDIF receiver, and the AD1835A
audio codec. The FLAG0 pin is used as a memory select for accessing the
SPI flash memory, and the FLAG3 pin is used for accessing the AD1835A’s
configuration registers.
The SPI chip select lines for the SPI flash memory and the AD1835A
audio codec connect to the processor via switch SW12 pins 1 and 3. The
default for SW12 is all positions ON. The switch disables the SPI devices on
the EZ-KIT Lite, allowing the same flag pins to be driven on the expan-
sion interface
All of the SPI signals are available externally via the expansion interface
connectors (J1–3), as well as the 0.1’ spaced header P2. The pinout of
these connectors can be found in “ADSP-21262 EZ-KIT Lite Schematic”
on page B-1.
Flag Pins
The processor has four general-purpose IO flag pins. Table 2-1 describes
the connection of each flag.
For information on how to disable the push buttons from driving the cor-
responding processor flag pin, see section “Push Button Enable Switch
(SW9)” on page 2-12.