Datasheet

System Architecture
2-8 ADSP-21262 EZ-KIT Lite Evaluation System Manual
Limits to the current and to the interface speed must be taken into consid-
eration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the used regulator. Additional circuitry
can also add extra loading to signals, decreasing their maximum effective
speed.
[
Analog Devices does not support and is not responsible for the
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory through a 6-pin interface. The JTAG emu-
lation port of the processor is also connected to the USB debugging
interface. When an emulator connects to the board at ZP4, the USB
debugging interface is disabled. This is not the standard connection of the
JTAG interface.
For information about the standard connection of the interface, see EE-68
published on the Analog Devices Web site (go to http://www.analog.com
and search for EE-68). For more information about the JTAG connector,
see “JTAG Header (ZP4)” on page 2-21. To learn more about available
emulators, contact Analog Devices (see “Product Information”).