Datasheet

ADSP-21262 EZ-KIT Lite Evaluation System Manual 2-13
ADSP-21262 EZ-KIT Lite Hardware Reference
Table 2-6 shows how to set up the clock multiply ratio using positions 3
and 4. By default, the processor increases the clock multiply ratio by 8,
setting the core clock to 200 MHz.
Loop-Back Test Switch (SW11)
The loop-back test switch (SW11) connects to GPO1 of the CS8416. The
functionality of GPO1 is programmable via SPI.
SPI Disable Switch (SW12)
The SPI interface switch (SW12) disables the SPI chip select lines con-
nected to the SPI flash memory and the AD1835A audio codec. The
switch also disables the
ADC_LRCLK and ADC_BCLK signals on the AD1835A
device. The switch allows a customer to re-use the same pins on the SPI
Table 2-5. Boot Mode Configuration
BOOTCFG1 Pin (Position 2) BOOTCFG0 Pin (Position 1) Boot Mode
OFF OFF SPI slave
OFF ON SPI master
ON OFF Parallel flash boot (default)
ON
ON Internal
Table 2-6. Core Clock Rate Configuration
CLKCFG1 (Position 4) CLKCFG0 (Position 3) Core to CLKIN Ratio
OFF OFF 3:1
OFF ON 16:1
ON OFF 8:1 (default)
ON
ON NA