Datasheet

ADSP-21479 EZ-Board Evaluation System Manual 1-11
Using ADSP-21479 EZ-Board
mation on how to initialize the registers after a reset, search the
VisualDSP++ online Help for “reset values”.
Parallel Flash Memory Interface
The parallel flash memory interface of the ADSP-21479 EZ-Board con-
tains a 4 MB (4M x 8 bits) Numonyx M29W320EB chip. Flash memory
is connected to the 8-bit data bus and address lines 0 through 21. Chip
enable is decoded by the MS1 select line (default) through switch SW13
position 2. See “External Port Enable Switch (SW13)” on page 2-12. The
address range for flash memory is 0x0400 0000 to 0x043F FFFF.
Flash memory is pre-loaded with boot code for the power-on-self test
(POST) program. For more information, refer to “Power-On-Self Test”
on page 1-22.
By default, the EZ-Board boots from the 8-bit parallel flash memory. The
processor boots from flash memory if the boot mode select switch (SW4) is
set to position 2; see “Boot Mode Select Switch (SW4)” on page 2-10.
Flash memory code can be modified. For instructions, refer to the online
Help and example program included in the EZ-Board installation
directory.
For more information about the parallel flash device, refer to the Num-
onyx Web site:
http://www.numonyx.com.
SPI Interface
The ADSP-21479 processor has two SPI ports, which can be accessed via
the digital peripheral interface (DPI) pins.