Datasheet

Shift Register Interface
1-14 ADSP-21479 EZ-Board Evaluation System Manual
Example programs are included in the EZ-Board installation directory to
demonstrate RTC functionality.
Shift Register Interface
The shift register (SR) of the ADSP-21479 processor can be used as a
serial to parallel data converter. The shift register module consists of an
18-stage serial shift register, 18-bit latch, and three-state output buffers.
The shift register and latch have separate clocks. Data is shifted into the
serial shift register on the positive-going transitions of the shift register
serial clock (SR_SCLK) input. The data in each flip-flop is transferred to the
respective latch on a positive-going transition of the shift register latch
clock (SR_LAT) input.
The shift register’s signals can be configured as follows.
• The SR_SCLK can come from any of the SPORT0–7 SCLK outputs,
PCGA/B clock, any of the DAI pins (1–8), and one dedicated pin
(SR_SCLK).
• The SR_LAT can come from any of SPORT0–7 frame sync outputs,
PCGA/B frame sync, any of the DAI pins (1–8), and one dedicated
pin (SR_LAT).
• The SR_SDI input can from any of SPORT0–7 serial data outputs,
any of the DAI pins (1–8), and one dedicated pin (
SR_SDI).
Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must come from the
same source, except in case of where SR_SCLK comes from PCGA/B or
SR_SCLK and SR_LAT come from PCGA/B.
If
SR_SCLK comes from PCGA/B, then SPORT0–7 generate SR_LAT and
SR_SDI signals. If SR_SCLK and SR_LAT come from PCGA/B, then SPORT0–7
generate
SR_SDI signal.