Datasheet

Audio Interface
1-16 ADSP-21479 EZ-Board Evaluation System Manual
for audio in and out. To use the differential connectors, change DIP
switches
SW15–18. A standard, off the shelf DB25 connector to XLR cables
is required to operate in this mode.
For more information, see “Audio In1 Left Selection Switch (SW15)” on
page 2-14 through “Audio In2 Left Selection Switch (SW18)” on
page 2-16, and “ADSP-21479 EZ-Board Schematic” on page B-1.
The processor interfaces with the codec via DAI and DPI pins. The DAI
pins can be configured to transfer serial data from the codec in Time-Divi-
sion Multiplexing (TDM) or Integrated Interchip Sound (I
2
S) mode. See
“DAI Interface” on page 2-3 for more information about the AD1939
connection to the DAI. The DPI interface pins can be configured to use
the SPI interface of the processor to set up the codec’s control registers.
See “DPI Interface” on page 2-4 for more information about the AD1939
connection to the DPI.
The master input clock (MCLK) of the codec is generated by the on-board
12.288 MHz oscillator. The internal PLL of the codec is used to generate
varying sample rates. The codec can be set up for 48 KHz, 96 KHz, or
192 KHz frequencies. The codec can run at these frequencies in both
TDM and I
2
S modes with all ADCs inputs and DACs outputs. To run
192 KHz with all ADCs and DACs in TDM mode, the codec must run in
dual-line TDM mode.
For information on how to configure the multi-channel codec, refer to the
product datasheet at:
http://www.analog.com/en/audiovideo-prod-
ucts/audio-codecs/ad1939/products/product.html
.
The EZ-Board is connected to the AD1939 codec in master mode. The
internal PLL drives the
ABCLK and ALRCLK clock signals out. Both clocks
are driven back to the codec’s
DBCLK and DLRCLK pins via the R257 and R258
resistors. The ABCLK and ALRCLK clocks that are driven by the codec also
connect to the processor’s serial ports via the DAI pins. Resistors
R262 and
R263 are used to feed the bit clock and frame sync signals of the processor’s