Datasheet

System Architecture
2-2 ADSP-21489 EZ-Board Evaluation System Manual
System Architecture
This section describes the processor’s configuration on the EZ-Board
(Figure 2-1).
The EZ-Board is designed to demonstrate the ADSP-21489 SHARC pro-
cessor capabilities. The processor runs at 400 MHz and has an I/O voltage
of 3.3V. The core voltage of the processor is 1.1V.
Figure 2-1. EZ-Board Block Diagram
ADSP-21489
Processor
400 MHz
176-lead LQFP
JTAG
Port
32 MB
SDRAM
(16Mb x 16)
25 MHz
Oscillator
DPI
Power
Regulation
AD1939
CODEC
Mic
In
Aud
In
(4)
Head
Out
Aud
Out
(8)
External
Port
4 MB
Flash
(4M x 16 )
DAI
CLK
TEMP
Sensor
MP
JTAG
IN
JTAG
CONN
Stand
Alone
Debug
Agent
ADM1032
SPI
Flash
16Mb
ADM3202
RS232
CONN
SPDIF
CIRC
SPDIF
IN
SPDIF
OUT
I2C
5V
PWR
IN
3.3V (Adjustable)
1.1V (Adjustable)
Sharc Expansion Interface II.
DAI = 0.1" Header
DPI = 0.1" Header
Ext. Port = High Speed Conn.
Ext. Port
DAI
DPI
PBs/
LEDs
MP
JTAG
OUT
WDT
DSP
Reset
ADM708
Reset
Supervisor
Jumper
2 MB
SRAM
(1M x 16)
Ext
Clock
Test Point/
Crystal