Blackfin® A-V EZ-Extender® Manual Revision 2.0, April 2006 Part Number 82-000870-01 Analog Devices, Inc. One Technology Way Norwood, Mass.
Copyright Information ©2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The A-V EZ-Extender is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice.
Regulatory Compliance The Blackfin A-V EZ-Extender has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark. The Blackfin A-V EZ-Extender had been appended to Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file.
CONTENTS PREFACE Product Overview ........................................................................... ix Purpose of This Manual .................................................................. xi Intended Audience .......................................................................... xi Manual Contents ........................................................................... xii What’s New in This Manual ...........................................................
CONTENTS A-V EZ-EXTENDER HARDWARE REFERENCE System Architecture ...................................................................... 2-2 Jumpers ........................................................................................ 2-7 Video Test Loopback Jumpers (JP1.1/2, JP1.3/4, JP1.5/6) ....... 2-7 Connector Voltage Selection Jumper (JP2) ............................... 2-7 TWI Source Selection Jumpers (JP3.3/5/7, JP3.4/6/8) ............. 2-7 PDWN Connection Jumper (JP3.9/10) ......................
CONTENTS PPI0_D Direction Setup Jumper (JP9.2/4/6) ......................... 2-14 Audio Loopback Jumpers (JP10.1/2, JP10.3/4) ...................... 2-14 A-V EXTENDER BILL OF MATERIALS A-V EZ-EXTENDER SCHEMATIC Title Page .................................................................................... B-1 Expansion Interface (1 and 2) ....................................................... B-2 Expansion Interface (3) ................................................................ B-3 Data Routing ...
CONTENTS viii Blackfin A-V EZ-Extender Manual
PREFACE Thank you for purchasing the Blackfin® A-V EZ-Extender®, Analog Devices, Inc. (ADI) extension board to the EZ-KIT Lite® evaluation system for ADSP-BF533, ADSP-BF537, and ADSP-BF561 Blackfin processors. The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture.
Product Overview The board extends the capabilities of the evaluation system by providing a connection to a video decoder, a video encoder, multiple camera evaluation boards, a flat panel display, and a 3-stereo input channel, 2-stereo output channel audio codec. The following is a list of the Blackfin A-V EZ-Extender interfaces. • Analog audio interface D D AD1836A Analog Devices 96 kHz audio codec five 3.
Preface • Flat panel display interface (FPDI) D D Connection to flat panel displays, for example, NL6448BC20-08E DF9B-31S-1V connector Before using any of the interfaces, follow the setup procedure in “A-V EZ-Extender Setup” on page 1-1. Example programs are available to demonstrate the capabilities of the Blackfin A-V EZ-Extender board. Purpose of This Manual The Blackfin A-V EZ-Extender Manual describes the operation and configuration of the components on the extension board.
Manual Contents Manual Contents The manual consists of: • Chapter 1, “A-V EZ-Extender Interfaces” on page 1-1 Provides basic board information. • Chapter 2, “A-V EZ-Extender Hardware Reference” on page 2-1 Provides information on the hardware aspects of the board. • Appendix A, “A-V Extender Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-Extender board.
Preface Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/technicalSupport • E-mail tools questions to processor.tools.support@analog.com • E-mail processor questions to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.
Product Information Product Information You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals). Analog Devices is online at http://www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. Related Documents For information on product related development software, see the following publications. Table 1.
Preface Table 2. Related VisualDSP++ Publications Title Description • • • ADSP-BF533 EZ-KIT Lite Evaluation System Manual ADSP-BF537 EZ-KIT Lite Evaluation System Manual ADSP-BF561 EZ-KIT Lite Evaluation System Manual Description of the EZ-KIT Lite features and usage. Note: For the ADSP-BF537 EZ-KIT Lite, there is additional Getting Started with ADSP-BF537 EZ-KIT Lite.
Notation Conventions Notation Conventions Text conventions used in this manual are identified and described as follows. Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu). {this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that.
Preface conventions, which apply only to specific chapters, may L Additional appear throughout this document.
Notation Conventions xviii Blackfin A-V EZ-Extender Manual
1 A-V EZ-EXTENDER INTERFACES This chapter provides a setup procedure for the Blackfin A-V EZ-Extender, an EZ-KIT Lite (ADSP-BF533, ADSP-BF537 or ADSP-BF561), and an evaluation module. The chapter also describes each of the evaluation interfaces the extender supports. The information is presented in the following order.
Analog Audio Interface 3. Set the jumpers on the A-V EZ-Extender board. Use the block diagram in Figure 2-1 on page 2-3 in conjunction with “Jumpers” on page 2-7. 4. Set the switches and jumpers on the EZ-KIT Lite board. If not already, familiarize yourself with the documentation and schematics of the EZ-KIT Lite (see “Related Documents”). Compare the expansion interface signals of the A-V EZ-Extender board with the signals of the EZ-KIT Lite board to ensure there is no contention.
A-V EZ-Extender Interfaces sample rate but allows simultaneous use of all input and output channels. To operate in I2S mode, the JP7.1/2 jumper must be installed. For more information, see “I2S Enable Jumper (JP7.1/2)” on page 2-13. The internal registers of the AD1836A audio codec can be programmed via the SPI port of the processor. (For information on how to program the configuration registers, refer to the AD1836A datasheet.
Camera Module Interfaces To use ADV7179 and ADV7183B, set up all of the jumpers related to the PPI data signals, frame sync signals, and clock signal. To program the internal register of the video devices, configure the two-wire interface signals (see “TWI Source Selection Jumpers (JP3.3/5/7, JP3.4/6/8)” on page 2-7). Finally, determine the source of the encoder or decoder reset (see “AV_RESET Source Jumper (JP9.1/3/5)” on page 2-14.
A-V EZ-Extender Interfaces Figure 1-1. Camera Orientation The P4 connector is designated for a Kodak camera sensor evaluation module. The interface has been tested with the Kodak KAC-9628 camera evaluation module. For information about Kodak camera sensors and evaluation boards, go to http://www.kodak.com. To connect the A-V EZ-Extender to a camera module, first determine the source of the PPI clock. To learn about possible clock settings, refer to “PPI Clock Setup Jumpers (JP4.1/2, JP4.3/4, JP4.5/6, JP4.
Flat Panel Display Interface Example programs demonstrating the capabilities of the camera module interface are included in the A-V EZ-Extender installation directory. Flat Panel Display Interface The flat panel display interface (FPDI) consists of a 31-pin DB9 connector linked to the PPI port and frame sync signals of the processor. For a general overview of the display interface connections, see Figure 2-1 on page 2-4. For more detailed information, see the “A-V EZ-Extender Schematic” on page B-1.
2 A-V EZ-EXTENDER HARDWARE REFERENCE This chapter describes the hardware design of the Blackfin A-V EZ-Extender. The following topics are covered. • “System Architecture” on page 2-2 Describes the configuration of the extension board and explains how the board components interface with the processor and EZ-KIT Lite. • “Jumpers” on page 2-7 Describes the function of the configuration jumpers.
System Architecture System Architecture A block diagram of the Blackfin A-V EZ-Extender is shown in Figure 2-1. Not shown in the diagram is the analog audio interface, which is a simple connection between the serial port of the processor and the AD1836A audio codec. The audio interface connects directly to SPORT0 of the expansion interface. In Figure 2-1, unidirectional buffers are show as triangle symbols, while bidirectional buffers are shown as two overlapping triangles.
A-V EZ-Extender Hardware Reference Figure 2-1.
System Architecture Table 2-1. Signals of Expansion Interface Connectors Net/Bus Name (Direction) A-V EZ-Extender Function Relevant Configuration Jumpers PPI0_D[0:15] VID_IN_D[0:15] Connects the processor’s PPI0 data pins to the or the VID_OUT_D[0:15] buses, depending on the jumper settings. This allows PPI0 to interface with all of the possible video interfaces on the board. This bus can be bidirectional; the direction can be fixed with a jumper or controlled by a flag pin. JP5.3/4, JP9.
A-V EZ-Extender Hardware Reference Table 2-1. Signals of Expansion Interface Connectors (Cont’d) Net/Bus Name (Direction) PPI1_D2 (Bi) PPI1_D3 A-V EZ-Extender Function Relevant Configuration Jumpers Multifunction net typically functions as the D2 pin of JP3.3/5/7, but also can function as the data signal for the pro- JP5.3/4, JP5.5/6 cessor’s two-wire interface (TWI). Used to program the internal configuration registers of most video interfaces.
System Architecture Table 2-1. Signals of Expansion Interface Connectors (Cont’d) Net/Bus Name (Direction) A-V EZ-Extender Function MISO The SPI serial input data signal used to read the control register of the AD1836A audio codec. (Output) RSCLK0 (Bi) RFS0 (Bi) DR0PRI (Output) DR0SEC (Output) TSCLK0 (Bi) TFS0 (Bi) DT0PRI Relevant Configuration Jumpers Processor’s SPORT0 receive clock signal connected to the serial clock on the digital side of the audio codec analog input.
A-V EZ-Extender Hardware Reference Jumpers Before using the Blackfin A-V EZ-Extender, follow the steps in “A-V EZ-Extender Setup” on page 1-1. Figure 2-2 shows the locations of all of the jumper headers. The jumper headers are divided to show the placement and rotation of each jumper. The jumpers are described by the pins of the header on which the jumpers can be placed. For example, JP3.4/6/8 refers to a single jumper that can be placed across pins 4 and 6, or pins 6 and 8, of JP3.
Jumpers Figure 2-2. Jumper Locations Table 2-2. Jumper Locations and Connector Voltages 2-8 Jumper Location Connector Voltage JP2.1/2 3.3V JP2.
A-V EZ-Extender Hardware Reference Table 2-3. Jumper Locations and TWI Interface Sources Jumper Pin Locations TWI Interface Source JP3.3/5 and JP3.4/6 Programmable flags JP3.5/7 and JP3.6/8 Two-wire interface of the processor PDWN Connection Jumper (JP3.9/10) Depending on the application, the PDWN pin of the OmniVision and Kodak cameras can be left floating or can be controlled by a flag pin (see Table 2-4). Table 2-4. PWDN Pin Connections JP3.
Jumpers Encoder HREF Connection Jumper (JP3.15/16) To connect the horizontal sync signal of the video encoder to the PPI0 frame sync signal of the processor, install the JP3.15/16 jumper; otherwise, the encoder’s horizontal reference is disconnected. Encoder VSYNC Connection Jumper (JP3.17/18) To connect the vertical sync signal of the video encoder to the PPI0 frame sync signal of the processor, install the JP3.17/18 jumper; otherwise, the encoder’s vertical sync is disconnected.
A-V EZ-Extender Hardware Reference Table 2-5. PPI Clock Setup Jumper Results Jumper Result JP4.1/2 Connects EXT_VID_CLK to an onboard 27 MHz oscillator. For more information about the EXT_VID_CLK signal, see the description of JP4.3/4. JP4.3/4 Connects PPI0_CLK to the EXT_VID_CLK net. The EXT_VID_CLK net is the external clock, which drives the input clock of all the camera module interface connectors, plus the flat panel display connector.
Jumpers Table 2-6. Video Out Data Bus Control Jumper Combinations JP5.3/4 JP5.5/6 VID_OUT Status Uninstalled Uninstalled VID_OUT, PPI1 are all not the state of JP9.2/4/6 Uninstalled Installed PPI1 drives VID_OUT Installed Uninstalled PPI0 drives VID_OUT Installed Installed PPI0 driven; PPI0 depends on drives VID_OUT, and VID_OUT drives PPI1 (loopback mode) PPI0_SYNC1 Direction Setup Jumper (JP6.
A-V EZ-Extender Hardware Reference Table 2-8. Setting Direction of PPI0_SYNC2 (JP6.2/4/6) Jumper Location PPI0_SYNC2 Direction JP6.2/4 Controlled by flag pin JP6.4/6 Input to processor Uninstalled Output from processor I 2 S Enable Jumper (JP7.1/2) When the JP7.1/2 jumper is installed, the SPORT signals are routed for I2S SPORT communication protocol mode. To accomplish this, the receive and transmit clocks of the processor are driven by the output clock of the AD1836A.
Jumpers AV_RESET Source Jumper (JP9.1/3/5) The source of the ICs reset on the A-V EZ-Extender is controlled by either a flag pin or a system reset; the latter also resetting the Blackfin processor (see Table 2-9). Table 2-9. Jumper Reset Sources Jumper Location Reset Source JP9.1/3 Flag pin multiplexed with PPI1_D11 JP9.3/5 System reset generator Uninstalled ICs are not reset PPI0_D Direction Setup Jumper (JP9.
A A-V EZ-EXTENDER BILL OF MATERIALS The bill of materials corresponds to “A-V EZ-Extender Schematic” on page B-1. Please check the latest schematic on the Analog Devices Web site: http://www.analog.com/Processors/Processors/DevelopmentTools/tec hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals. Ref. Qty. Description Reference Designator Manufacturer Part Number 1 1 SN74AHC1G00 SOT23-5 U9 TI SN74AHC1G00DBVR 2 1 12.288MHZ OSC003 U18 DIGI-KEY SG-8002CA-PCC-ND (12.
Ref. Qty.
A-V Extender Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 25 1 IDC 13x2RA IDC13x2_F_RA J6 SAMTEC SSW-113-02-F-D-RA 26 1 3.5MM 5xAUDIO_JACK CON035 J5 FOXCON JA3333F-R55 27 1 IDC 3X1 IDC3X1 JP2 FCI 90726-403HLF 28 1 IDC 2X2 IDC2X2 JP10 SULLINS PBC02DAAN 29 8 0.22UF 25V 10% 0805 C73,C85,C101, C112,C120-121, C135,C138 AVX 08053C224FAT 30 2 33 1/10W 5% 0805 R49,R52 VISHAY CRCW080533R0JNEA 31 1 1.
Ref. Qty. Description Reference Designator Manufacturer Part Number 42 1 76.8K 1/10W 1% 0805 R38 DIGI-KEY 311-76.8KCRTR-ND 43 1 1.2K 1/16W 5% 0402 R42 PANASONIC ERJ-2GEJ122X 44 57 0.1UF 16V 10% 0603 C1,C4,C7-8,C10-15, AVX C17,C19,C22-23, C26,C30,C32-34, C37-38,C40, C43-44,C46-49, C51-57,C60-69, C75-76,C78,C81, C99,C115,C124, C130-132,C144-145 0603YC104KAT2A 45 11 0.
A-V Extender Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 53 1 10 1/10W 5% 0603 R143 VISHAY CRCW060310R0JNEA 54 6 1K 1/10W 5% 0603 R13-14,R18-19, R23-24 DIGI-KEY 311-1.0KGRTR-ND 55 4 237.0 1/10W 1% 0603 R64,R70,R106,R110 DIGI-KEY 311-237HRTR-ND 56 4 750.0K 1/10W 1% 0603 R65,R69,R127,R129 DIGI-KEY 311-750KHRTR-ND 57 6 11.0K 1/10W 1% 0603 R82,R90,R93-94, R123,R126 DIGI-KEY 311-11.0KHRTR-ND 58 12 5.
Ref. Qty. Description Reference Designator Manufacturer Part Number 66 10 1000PF 50V 5% 0603 C9,C24,C72,C86, C93,C100,C103, C111,C117,C119 PANASONIC ECJ-1VC1H102J 67 6 220PF 50V 5% 0603 C87,C94-96, C125-126 PANASONIC ECJ-1VC1H221J 68 6 680PF 50V 5% 0603 C84,C88-90, C122-123 PANASONIC ECJ-1VC1H681J 69 6 2200PF 50V 5% 0603 C102,C113-114, C116,C140,C142 PANASONIC ECJ-1VB1H222K 70 7 33.0 1/10W 1% 0603 R5,R8,R33,R68, R142,R144-145 DIGI-KEY 311-33.0HRTR-ND 71 6 2.
A B C D 1 1 2 2 Blackfin A-V EZ-Extender Schematic 3 3 ANALOG DEVICES 4 Title Size A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD BLACKFIN A-V EZ-EXTENDER TITLE Board No. C Date 20 Cotton Road Rev A0193-2004 2.
A B C 3.
A B C D EXPANSION INTERFACE (TYPE B) 5V 3.
A B C D PPI0_D[15:0] RN1 1 1 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 8 PPI0_D0 7 PPI0_D1 6 PPI0_D2 PPI0_D0 47 5 PPI0_D3 PPI0_D1 46 PPI0_D2 44 PPI0_D3 43 PPI0_D4 41 PPI0_D5 40 PPI0_D6 38 PPI0_D7 37 PPI0_D8 36 VID_OUT_D[15:0] U10 U11 VID_IN_D0 VID_IN_D[15:0] VID_IN_D1 3 VID_IN_D2 5 VID_IN_D3 2 2 6 VID_IN_D4 8 VID_IN_D5 9 VID_IN_D6 11 VID_IN_D7 12 VID_IN_D8 13 VID_IN_D9 14 VID_IN_D10 16 VID_IN_D11 17 VID_IN_D12 19 VID_IN_D13 20 VID_IN_D14 22 V
A B C D Video In Frame Sync Setup U14 3.3V 2 1B1 3 1B2 5 1B3 6 1B4 8 1B5 9 1B6 11 1B7 12 1B8 13 2B1 14 2B2 16 2B3 17 2B4 19 2B5 20 2B6 22 2B7 23 2B8 VID_IN_SYNC1_HREF 1 R55 22 0805 VID_IN_SYNC2_VSYNC 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 47 PPI Clock Setup PPI0_SYNC1 46 3.
A B C CONN_SUPPLY D Micron Interface Kodak Interface VID_IN_D[15:0] J6 VID_IN_D1 2 1 VID_IN_D0 VID_IN_D3 4 3 VID_IN_D2 VID_IN_D5 6 5 VID_IN_D4 VID_IN_D7 8 7 VID_IN_D6 VID_IN_D9 10 9 VID_IN_D8 12 11 1 AV_RESET SDA EXT_VID_CLK 14 13 16 15 18 17 20 19 22 21 24 23 26 25 5V 3.3V Micron Interface P4 J4 J6 CONN_SUPPLY TP13 1 JP2 1 VID_IN_SYNC1_HREF 2 3 VID_IN_SYNC2_VSYNC OmniVision Interface SCL IDC3X1 1 Jumper C44 0.
VIDEO_AVIN5 2 3 4 5 6 VIDEO_DAC_A VIDEO_DAC_C VIDEO_DAC_B DAC_A VIDEO_AVIN4 JP1 1 C DAC_B VIDEO_AVIN1 B DAC_C A IDC3X2_SMT (WHITE) OUT D DAC A DAC B DAC C Composite Video CVSB CVSB C Component Video G B R Differential Component Video Y U V S Video Y C (RED) IN AVIN1 AVIN4 1 AVIN5 1 R13 1K 0603 A3V VIDEO_DAC_A U3 5 4 L1 0.68UH 0805 L4 2.2UH 0805 J7 L7 0.68UH 0805 1 3 3.
A B C D 3.3V 3.3V AVIN1 AVIN4 AVIN5 Composite Video CVBS CVBS CVBS Differential Component Video Y S Video Y V VIDEO DECODER U R10 10K 0603 C R34 10K 0603 DNP 1 1 OE OUT R45 10K 0603 R3 10K 0603 U2 27MHZ_CLK R5 33.0 0603 U1 R35 10K 0603 DNP 1 3 29 28 27MHZ OSC003 XTAL XTAL1 P15 P14 P13 66 67 SDA 68 SCL ALSB P12 SDA P11 SCLK P10 P9 64 AV_RESET 36 RESET P8 PWRDN P7 P6 J7 65 R15 0 0603 CON024 7 AVIN1 C19 0.
A B C D I2S_EN I2S_EN 2 RFS0 U30 4 TFS0 RSCLK0 SN74LVC1G125 SOT23-5 R145 33.0 0603 1 1 U29 R144 33.0 0603 2 4 3.3V TSCLK0 SN74LVC1G125 SOT23-5 R60 10K 0603 1 1 OUT1 (BLUE) R68 33.0 0603 U18 3 OUT OE IN1 (BLACK) AD1836_CLK OUT2 (LIME) 12.288MHZ OSC003 3.3V AUDIO CODEC 3.3V 3.3V 5V IN2 (YELLOW) OUT3 (PINK) A5V R141 10K 0603 FER9 600 1206 JP7 I2S_EN DR0PRI 1 2 3 4 5 DR0SEC 1 R107 10K 0603 6 47 R142 33.
A B C 1 R100 5.49K 0603 R93 11.0K 0603 D 1 C106 100PF 0603 R92 3.32K 0603 OUT1R- C107 330PF 0603 2 U23 1 DAC1 RIGHT 3 R86 5.49K 0603 C89 680PF 0603 AD8606ARZ SOIC8 R85 1.65K 0603 R102 604.0 0603 OUT1R+ CT8 10UF CAP002 DAC1_RIGHT R79 2.74K 0603 C95 220PF 0603 R109 49.9K 0603 C113 2200PF 0603 2 2 AGND R99 5.49K 0603 R90 11.0K 0603 C105 100PF 0603 R91 3.32K 0603 OUT1L- C104 330PF 0603 6 U23 7 DAC1 LEFT 5 R83 5.49K 0603 C88 680PF 0603 AD8606ARZ SOIC8 R84 1.65K 0603 R104 604.
A B C D 1 1 R132 5.49K 0603 R126 11.0K 0603 R101 5.49K 0603 C136 100PF 0603 R125 3.32K 0603 R94 11.0K 0603 OUT2R- C109 100PF 0603 R95 3.32K 0603 OUT3R- C137 330PF 0603 2 C108 330PF 0603 U25 1 DAC2 RIGHT 7 DAC3 RIGHT 3 R119 5.49K 0603 C123 680PF 0603 5 AD8606ARZ SOIC8 R118 1.65K 0603 U22 6 R133 604.0 0603 R87 5.49K 0603 CT15 10UF CAP002 OUT2R+ C90 680PF 0603 AD8606ARZ SOIC8 R88 1.65K 0603 R103 604.0 0603 OUT3R+ CT9 10UF CAP002 DAC2_RIGHT R113 2.
A B CT6 10UF CAP002 FER6 600 0603 1 R77 5.76K 0603 C R73 5.76K 0603 D CT5 10UF CAP002 FER5 600 0603 ADC1_LEFT R76 5.76K 0603 R61 5.76K 0603 ADC2_LEFT 1 C83 120PF 0603 C92 100PF 0603 C91 100PF 0603 R70 237.0 0603 U21 2 C71 120PF 0603 2 1 1 IN1L- AGND IN2L2 AGND 3 3 AD8606ARZ SOIC8 R63 5.76K 0603 AD8606ARZ SOIC8 C86 1000PF 0603 R62 5.76K 0603 C77 100PF 0603 R67 5.76K 0603 R72 5.76K 0603 ADC1 LEFT C74 120PF 0603 C72 1000PF 0603 R69 750.0K 0603 R64 237.
I INDEX A B AD1836A audio codecs, 1-2, 2-5, 2-6, 2-10, 2-13 ADSP-BF533/37/61 processors flag pins, 2-5, 2-9, 2-14 parallel peripheral interfaces (PPI0-1), 1-2, 1-3, 1-6 PPI0-1 data pins, 2-4 PPI frame sync signals, 1-6, 2-9, 2-10 serial peripheral interface (SPI), 1-3 SPORT signals, 2-13 ADV7179 video encoders connections, 1-3 HREF connection jumper, 2-10 VSYNC connection jumper, 2-10 ADV7183B video decoders connections, 1-3 HSYNC disconnect jumper, 2-9 output enable jumper, 2-10 VSYNC connection jumper
INDEX EXT_VID_CLK pin, 2-11 EZ-KIT Lites, parallel peripheral interfaces (PPI0-1), 2-2, 2-5 F flag pins, ADSP-BF533/37/61 processors, 2-5, 2-9, 2-14 FLAG_SCL_DIR_CTRL net, 2-5 FLAG_SDA net, 2-5 flat panel display interface, See FPDI FODD (OmniVision control) signal, 2-10 FPDI connections, -xi, 2-2 HS signal, 2-4, 2-5 overview, 1-6 VS signal, 2-4, 2-5 frame sync signals, 2-2, 2-13 G general-purpose flags, 2-10, 2-12, 2-14 H HREF connection jumper, 2-10 signal, 2-4 HS signal, 2-4, 2-5 HSYNC disconnect jum
INDEX JP8.2/4/6 (video out SYNC select) jumper, 2-4, 2-5, 2-13 JP8.7/8 (video out SYNC enable) jumper, 2-4, 2-5, 2-13 JP9.1/3/5 (reset) jumper, 2-14 JP9.
INDEX SCK net, 2-5 serial peripheral interface, See SPI setup, of this EZ-Extender, 1-1 SNAPSHOT_FODD disconnect jumper, 2-10 SNAPSHOT_FODD_SSEL net, 2-5 SNAPSHOT (Kodak camera) signal, 2-10 SPI serial clock (SCK), 2-5 serial input data signal (MISO), 2-6 serial output data signal (MOSI), 2-5 SPORT configuring for I2S mode, 2-13 data connection jumpers, 2-13 data input pins, 2-13 SPORT0 connections, 1-2, 2-2 receive clock signal (RSCLK0), 2-6 receive frame SYNC signal (RFS0), 2-6 transmit clock signal (TSC
