Quad Parametric Measurement Unit with Integrated 16-Bit Level Setting DACs AD5522 Data Sheet FEATURES APPLICATIONS Quad parametric measurement unit (PMU) FV, FI, FN (high-Z), MV, MI functions 4 programmable current ranges (internal RSENSE) ±5 μA, ±20 μA, ±200 μA, and ±2 mA 1 programmable current range up to ±80 mA (external RSENSE) 22.
AD5522 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Calibration................................................................................... 38 Applications ....................................................................................... 1 Additional Calibration ............................................................... 39 Functional Block Diagram ................................................
Data Sheet AD5522 REVISION HISTORY 5/12—Rev. D to Rev. E Change to MV Transfer Function, Table 11 ................................33 2/11—Rev. C to Rev. D Changes to Measure Current, Gain Error Tempco Parameter.... 6 Changes to Force Current, Common Mode Error (Gain = 5) and Common Mode Error (Gain = 10) Parameters ..................... 7 Changes to Figure 5.........................................................................13 Changes to Figure 6.......................................................
AD5522 Data Sheet GENERAL DESCRIPTION The AD5522 is a high performance, highly integrated parametric measurement unit consisting of four independent channels. Each per-pin parametric measurement unit (PPMU) channel includes five 16-bit, voltage output DACs that set the programmable input levels for the force voltage inputs, clamp inputs, and comparator inputs (high and low). Five programmable force and measure current ranges are available, ranging from ±5 µA to ±80 mA.
Data Sheet AD5522 AVSS AGND VREF REFGND 16 16 16 X1 REG M REG C REG 16 16 16 CCOMP0 DGND DVCC AVDD CH0 16-BIT CLH DAC 16 X2 REG EN CLH ×2 OFFSET DAC X1 REG M REG C REG – 16-BIT 16 FIN DAC FIN INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) SW1 + + AGND X2 REG FOH0 FORCE AMPLIFIER MEASVH (Hi-Z) ×6 SW5 – RSENSE SW2 X1 REG M REG C REG CFF0 SW3 ×2 ×6 16 16 16 EXTFOH0 16 X2 REG 16-BIT CLL DAC ×2 VMID TO CENTER I RANGE SW10 ×2 EXTMEASIH0 + – SW12 AGND 16 16 16
AD5522 Data Sheet SPECIFICATIONS AVDD ≥ 10 V; AVSS ≤ −5 V; |AVDD − AVSS| ≥ 20 V and ≤ 33 V; DVCC = 2.3 V to 5.25 V; VREF = 5 V; REFGND = DUTGND = AGND = 0 V; gain (M), offset (C), and DAC offset registers at default values; TJ = 25°C to 90°C, unless otherwise noted. (FV = force voltage, FI = force current, MV = measure voltage, MI = measure current, FS = full scale, FSR = full-scale range, FSVR = full-scale voltage range, FSCR = full-scale current range.) Table 1.
Data Sheet Parameter Measure Current Ranges2 AD5522 Min Typ 1 Max Unit ±80 µA µA µA mA mA ±5 ±20 ±200 ±2 Noise Spectral Density (NSD)2 FORCE CURRENT Voltage Compliance, FOHx2 Voltage Compliance, EXTFOHx2 Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error Common-Mode Error (Gain = 5) Common-Mode Error (Gain = 10) Force Current Ranges 400 AVSS + 4 AVSS + 3 −0.5 nV/√Hz AVDD − 4 AVDD − 3 +0.5 +0.02 +0.01 +0.
AD5522 Parameter CURRENT CLAMPS Clamp Accuracy CLL to CLH2 Data Sheet Min Typ 1 Programmed clamp value Programmed clamp value 5 Max Unit Test Conditions/Comments Programmed clamp value ± 10 Programmed clamp value ± 20 % FSC MI gain = 10, clamp current scales with selected range MI gain = 5, clamp current scales with selected range 1.
Data Sheet Parameter GUARDx PIN Output Voltage Span Output Offset Short-Circuit Current Maximum Load Capacitance2 Output Impedance Tristate Leakage Current2 Slew Rate2 Alarm Activation Time2 FORCE AMPLIFIER2 Slew Rate Gain Bandwidth Max Stable Load Capacitance AD5522 Min Typ 1 Max 22.5 −10 −15 +10 +15 100 85 −30 +30 5 200 0.4 1.
AD5522 Parameter DIE TEMPERATURE SENSOR Accuracy2 Output Voltage at 25°C Output Scale Factor2 Output Voltage Range2 INTERACTION AND CROSSTALK2 DC Crosstalk (FOHx) Data Sheet Typ 1 Max Unit 3 °C V mV/°C V 0.05 0.65 mV DC Crosstalk (MEASOUTx) 0.05 0.65 mV DC Crosstalk Within a Channel 0.05 SPI INTERFACE LOGIC INPUTS Input High Voltage, VIH Min ±7 1.5 4.6 0 1.7/2.
Data Sheet AD5522 Parameter Power Supply Sensitivity2 ΔForced Voltage/ΔAVDD ΔForced Voltage/ΔAVSS ΔMeasured Current/ΔAVDD ΔMeasured Current/ΔAVSS ΔForced Current/ΔAVDD ΔForced Current/ΔAVSS ΔMeasured Voltage/ΔAVDD ΔMeasured Voltage/ΔAVSS ΔForced Voltage/ΔDVCC ΔMeasured Current/ΔDVCC ΔForced Current/ΔDVCC ΔMeasured Voltage/ΔDVCC 1 2 Min Typ 1 Max Unit −80 −80 −85 −75 −75 −75 −85 −80 −90 −90 −90 −90 Test Conditions/Comments From dc to 1 kHz dB dB dB dB dB dB dB dB dB dB dB dB Typical specifications
AD5522 Parameter 1, 2, 3 t16 t17 t18 t19 5, 6 Data Sheet DVCC, Limit at TMIN, TMAX 2.3 V to 2.7 V 2.7 V to 3.6 V 4.5 V to 5.25 V 1.8 1.2 0.9 670 700 750 400 400 400 60 45 25 Unit µs min µs max ns min ns max Description RESET pulse width low RESET time indicated by BUSY low Minimum SYNC high time in readback mode SCLK rising edge to SDO valid; DVCC = 5 V to 5.25 V Guaranteed by design and characterization; not production tested.
Data Sheet AD5522 Circuit and Timing Diagrams DVCC 200µA 2.2kΩ 50pF VOH(MIN) – VOL(MAX) 2 200µA 06197-004 VOL CLOAD TO OUTPUT PIN CLOAD 50pF 06197-003 RLOAD TO OUTPUT PIN IOL IOH Figure 4. Load Circuit for SDO, BUSY Timing Diagram Figure 3.
AD5522 Data Sheet SCLK 58 29 t19 t18 SYNC DB28 (N) DB0 (N + 1) DB23/ DB28 (N + 1) DB0 (N) INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB23/ DB28 (N + 1) SDO DB0 (N + 1) 06197-006 SDI SELECTED REGISTER DATA CLOCKED OUT UNDEFINED Figure 6.
Data Sheet AD5522 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage, AVDD to AVSS AVDD to AGND AVSS to AGND VREF to AGND DUTGND to AGND REFGND to AGND DVCC to DGND AGND to DGND Digital Inputs to DGND Analog Inputs to AGND Storage Temperature Range Operating Junction Temperature Range (J Version) Reflow Soldering Junction Temperature Rating 34 V −0.3 V to +34 V +0.3 V to −34 V −0.3 V to +7 V AVDD + 0.3 V to AVSS − 0.3 V AVDD + 0.3 V to AVSS − 0.3 V −0.3 V to +7 V −0.3 V to +0.
AD5522 Data Sheet EXTFOH1 AVSS MEASOUT3 MEASOUT2 MEASOUT1 MEASOUT0 AVSS SYS_FORCE AGND SYS_SENSE VREF REFGND AVDD 80 79 78 77 76 75 74 DUTGND CGALM SPI/LVDS RESET TMPALM AVSS EXTFOH0 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 73 72 71 70 69 68 67 66 65 64 63 62 61 60 AVDD 1 CFF0 2 PIN 1 CCOMP0 3 AVDD 59 CFF1 58 CCOMP1 EXTMEASIH0 4 57 EXTMEASIH1 EXTMEASIL0 5 56 EXTMEASIL1 FOH1 FOH0 6 55 GUARD0 7 54 GUARD1 GUARDIN0/DUTGND0 8 53 GUARDIN1/DUTGND1 52 MEASVH1 51
Data Sheet Pin No.
AD5522 Data Sheet Pin No. 49 52 53 Mnemonic MEASVH3 MEASVH1 GUARDIN1/ DUTGND1 54 55 56 57 58 59 GUARD1 FOH1 EXTMEASIL1 EXTMEASIH1 CCOMP1 CFF1 61 EXTFOH1 63 MEASOUT3 64 MEASOUT2 65 MEASOUT1 66 MEASOUT0 68 70 71 72 73 SYS_FORCE SYS_SENSE REFGND VREF DUTGND 75 SPI/LVDS 76 CGALM 77 TMPALM 78 RESET 80 EXTFOH0 Description DUT Voltage Sense Input (High Sense) for Channel 3. DUT Voltage Sense Input (High Sense) for Channel 1.
80 79 78 77 76 75 74 AVDD CCOMP2 CFF2 EXTMEASIL2 EXTMEASIH2 GUARD2 FOH2 MEASVH2 GUARDIN2/DUTGND2 AGND AGND GUARDIN0/DUTGND0 MEASVH0 FOH0 GUARD0 EXTMEASIL0 CCOMP0 EXTMEASIH0 CFF0 AD5522 AVDD Data Sheet 73 72 71 70 69 68 67 66 65 64 63 62 61 EXTFOH0 1 PIN 1 AVSS 2 60 EXTFOH2 59 AVSS RESET 3 58 BUSY TMPALM 4 57 SCLK CGALM 5 56 CPOL0/SCLK SPI/LVDS 6 55 CPOH0/SDI 54 SDI AVDD 7 AD5522 DUTGND 8 53 SYNC TOP VIEW EXPOSED PAD ON TOP VREF 9 REFGND 10 52 CPOL1/SYNC 51 D
AD5522 Data Sheet Pin No.
Data Sheet Pin No. 46 Mnemonic CPOL2/CPO0 47 48 DVCC LOAD 49 50 SDO CPOH1/SDO 51 52 53 54 55 DGND CPOL1/SYNC SYNC SDI CPOH0/SDI 56 CPOL0/SCLK 57 SCLK 58 BUSY 60 EXTFOH2 62 CFF2 63 64 65 66 67 68 CCOMP2 EXTMEASIH2 EXTMEASIL2 FOH2 GUARD2 GUARDIN2/ DUTGND2 69 72 73 MEASVH2 MEASVH0 GUARDIN0/ DUTGND0 74 75 76 77 78 79 GUARD0 FOH0 EXTMEASIL0 EXTMEASIH0 CCOMP0 CFF0 AD5522 Description Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface.
AD5522 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.0020 TA = 25°C NOM: AVDD = +16.5V, AVSS = –16.6V, OFFSET DAC = 0XA492 HIGH: AVDD = +28V, AVSS = –5V, OFFSET DAC = 0X0 LOW: AVDD = +10V, AVSS = –23V, OFFSET DAC = 0xEDB7 0.8 0.0015 0.6 LINEARITY (% FSR) 0.2 0 –0.2 –0.4 0.0010 0.0005 –0.6 0 06197-010 DNL INL –0.8 –1.0 0 10,000 20,000 30,000 40,000 50,000 –0.0005 60,000 0 10,000 20,000 CODE 30,000 40,000 50,000 60,000 CODE Figure 10. Force Voltage Linearity vs.
Data Sheet AD5522 0.005 0.2 AVDD = +15.5V, AVSS = –15.5V, OFFSET DAC = 0xA492 AVDD = +28V, AVSS = –5V, OFFSET DAC = 0x0 AVDD = +10V, AVSS = –23V, OFFSET DAC = 0xED87 0.001 0 –0.001 –0.2 –0.4 EXTFOHx CFFx FOHx EXTMEASIHx EXTMEASILx MEASVHx GUARDINx/DUTGNDx COMBINED LEAKAGE –0.6 –0.8 –1.0 06197-142 –0.002 –0.003 10,000 20,000 30,000 40,000 50,000 60,000 –1.2 25 35 45 55 85 95 0.15 1.0 TA = 25°C V = 0V EXTFOHx CFFx FOHx EXTMEASIHx EXTMEASILx MEASVHx GUARDINx/DUTGNDx COMBINED LEAKAGE 0.
AD5522 Data Sheet 0 0 –10 –10 –20 –20 VSS VDD –40 –50 VCC –60 –40 ACPSRR (dB) –60 –100 100 1k 10k FREQUENCY (Hz) 1M 100k 06197-019 –90 –90 –110 10 1M 100k 0 0 –10 –10 VSS –20 –20 VSS –30 –30 VDD VDD ACPSRR (dB) –40 –40 –50 VCC –60 –70 –50 VCC –60 –70 –90 –90 –100 –100 –110 100 1k 10k FREQUENCY (Hz) 1M 100k –120 10 100 1k 10k FREQUENCY (Hz) 1M 100k 06197-021 –80 –80 06197-119 ACPSRR (dB) 1k 10k FREQUENCY (Hz) Figure 25.
Data Sheet AD5522 0 TA = 25°C –10 –20 –30 1 ACPSRR (dB) –40 FOH0 VSS –50 –60 VCC –70 MEASOUT0 VDD 2 –80 –90 4 LOAD 06197-023 –100 –120 10 100 1k 10k FREQUENCY (Hz) 1M 100k 06197-122 –110 B B CH2 100mV W CH4 5.00V CH1 Pk-Pk 39.00mV CH2 Pk-Pk 325.8mV CH1 20.0mV Figure 28. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency (MI Gain = 10, MEASOUT Gain = 0.2) W M4.00µs T 10.0000µs Figure 31.
AD5522 Data Sheet TA = 25°C SYNC 4 3 1 2 BUSY FOHx VICTIM MEASOUTx VICTIM FOH0 1 TRIGGER 4 B CH1 10.0mV W CH2 50.0mV CH3 5.00V CH4 5.00V CH2 Pk-Pk 14.38mV B W 06197-129 06197-026 MEASOUTx ATTACK 3 M100µs T 200.000µs CH1 50.0mV Figure 34. Shorted DUT AC Crosstalk, Victim PMU in FVMI Mode (±200 μA Range) B W CH3 5.00V BW CH4 5.00V BW M800ns CH4 T 2.40000µs 2.10V Figure 37. Range Change, PMU0, ±2 mA to ±5 μA, CLOAD = 1 nF, RLOAD = 620 kΩ, FV = 3 V MEASOUTx VOLTAGE (V) 1.80 SYNC 1.
Data Sheet 4 AD5522 SYNC SYNC 4 BUSY 3 BUSY 3 MEASOUTx (MI) FOH0 2 1 FOHx CH1 100.0mV B W CH3 5.00V BW CH4 5.00V BW M2.00µs CH4 T 6.00000µs 06197-135 06197-132 1 2.10V CH1 2.00V CH3 5.00V CH2 2.00V CH4 5.00V M5.0µs CH1 3.84V Figure 43. FV Settling, 0 V to 5 V, ±2 mA Range, CLOAD = 220 pF, CCOMPx = 100 pF, RLOAD = 5.6 kΩ Figure 40.
AD5522 Data Sheet SYNC 4 BUSY 3 MEASOUTx (MI) 2 FOHx 06197-138 1 CH1 2.00V CH3 5.00V CH2 10.0V CH4 5.00V M10.0µs CH1 3.20V Figure 46. FV Settling, 0 V to 5 V, ±200 μA Range, CLOAD = 220 pF, CCOMPx = 100 pF, RLOAD = 27 kΩ Rev.
Data Sheet AD5522 TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in mV or % FSR. Gain Error Gain error is the difference between full-scale error and zeroscale error. It is expressed in % FSR. Gain Error = Full-Scale Error − Zero-Scale Error where: Full-Scale Error is the difference between the actual voltage and the ideal voltage at full scale.
AD5522 Data Sheet THEORY OF OPERATION The AD5522 is a highly integrated, quad per-pin parametric measurement unit (PPMU) for use in semiconductor automated test equipment. It provides programmable modes to force a pin voltage and measure the corresponding current (FVMI) and to force a pin current and measure the corresponding voltage (FIMV). The device is also capable of all other combinations, including force high-Z and measure high-Z. The PPMU can force or measure a voltage range of 22.5 V.
Data Sheet AD5522 where: FI is the forced current. RSENSE is the selected sense resistor. MI_Amplifier_Gain is the gain of the measure current instrumentation amplifier. This gain can be set to 5 or 10 via the serial interface. When the AD5522 is placed in high-Z mode, the clamp circuit is always configured to monitor the measure current signal (irrespective of which high-Z mode is selected, high-Z V or high-Z I). At this time, the clamp circuit is also comparing to the voltage clamp levels.
AD5522 Data Sheet MEASURE CURRENT GAINS VREF = 3.5 V results in a ±7.87 V range. Using a gain setting of 10, there is ±0.785 V maximum across RSENSE, resulting in current ranges of ±3.92 μA, ±15.74 μA, and so on (including overrange of ±12.5% to allow for error correction). The measure current amplifier has two gain settings, 5 and 10. The two gain settings allow users to achieve the quoted/specified current ranges with large or small voltage swing.
Data Sheet AD5522 CHOOSING POWER SUPPLY RAILS MEASURE OUTPUT (MEASOUTx PINS) As noted in the Specifications section, the minimum supply variation across the part |AVDD − AVSS| ≥ 20 V. For the AD5522 circuits to operate correctly, the supply rails must take into account not only the force voltage range, but also the internal DAC minimum voltage level, as well as headroom and so on. The DAC amplifier gains VREF by 4.5, and the offset DAC centers that range about some chosen point.
AD5522 Data Sheet When configured as DUTGND per channel, this dual function pin is no longer connected to the input of the guard amplifier. Instead, it is connected to the low end of the instrumentation amplifier (SW14a), and the input of the guard amplifier is connected internally to MEASVHx (SW13a). MEASVH[0:3] + – a SW13 AGND SW14 a b GUARD GUARD[0:3] AMP GUARDIN[0:3]/ DUTGND[0:3] + – b DUTGND MEASURE VOLTAGE IN-AMP 06197-029 + ×1 – DUT SW16 Figure 49.
Data Sheet AD5522 TEMPERATURE SENSOR SYSTEM FORCE AND SENSE SWITCHES An on-board temperature sensor monitors die temperature. The temperature sensor is located at the center of the die. If the temperature exceeds the factory specified value (130°C) or a user programmable value, the device protects itself by shutting down all channels and flagging an alarm through the latched, open-drain TMPALM pin.
AD5522 Data Sheet DAC LEVELS Each channel contains five dedicated DAC levels: one for the force amplifier, one each for the clamp high and clamp low levels, and one each for the comparator high and comparator low levels. The power supplies should be selected to support the required range and should take into account amplifier headroom and footroom and sense resistor voltage drop (±4 V).
Data Sheet AD5522 The calibration engine is engaged only when data is written to the X1 register and for some PMU writes (see Table 18). The calibration engine is not engaged when data is written to the M or C register. This has the advantage of minimizing the initial setup time of the device. To calculate a result that includes new M or C data, a write to X1 is required.
AD5522 Data Sheet Table 14. References Suggested For Use with AD5522 1 Part No. ADR435 ADR445 ADR431 ADR441 1 Voltage (V) 5 5 2.5 2.5 Initial Accuracy % ±0.04 ±0.04 ±0.04 ±0.04 Ref Out TC (ppm/°C) 1 1 1 1 Ref Output Current (mA) 30 10 30 10 Supply Voltage Range (V) +7 to +18 +5.5 to +18 +4.5 to +18 +3 to +18 Package MSOP, SOIC MSOP, SOIC MSOP, SOIC MSOP, SOIC Subset of the possible references suitable for use with the AD5522. Visit www.analog.com for more options.
Data Sheet AD5522 Calibration Example The calibration procedure for the force and measure circuitry is as follows: Nominal offset coefficient = 32,768 Nominal gain coefficient = 65,535 1. Calibrate the force voltage (2 points). In FV mode, write zero scale to the FIN DAC. Connect SYS_FORCE to FOHx and SYS_SENSE to MEASVHx, and close the internal force/sense switch (SW7). For example, the gain error = 0.5%, and the offset error = 100 mV. Gain error (0.5%) calibration: 65,535 × 0.
AD5522 Data Sheet CIRCUIT OPERATION The forced voltage can be calculated as follows: FORCE VOLTAGE (FV) MODE Forced Voltage at DUT = VOUT Most PMU measurements are performed in force voltage/measure current (FVMI) mode, for example, when the device is used as a device power supply, or in continuity or leakage testing. In force voltage (FV) mode, the voltage forced is mapped directly to the DUT.
Data Sheet AD5522 FORCE CURRENT (FI) MODE In force current (FI) mode, the voltage at the FIN DAC is converted to a current and is applied to the DUT. The feedback path is the measure current amplifier, feeding back the voltage measured across the sense resistor. MEASOUTx reflects the voltage measured across the DUT (see Figure 55). where: FI is the forced current. RSENSE is the selected sense resistor. MI_Amplifier_Gain is the gain of the measure current instrumentation amplifier.
AD5522 Data Sheet SERIAL INTERFACE The AD5522 provides two high speed serial interfaces: an SPIcompatible interface operating at clock frequencies up to 50 MHz and an EIA-644-compliant LVDS interface. To minimize both the power consumption of the device and the on-chip digital noise, the serial interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. SPI INTERFACE The serial interface operates from a 2.3 V to 5.25 V DVCC supply range.
Data Sheet AD5522 BUSY also goes low during a power-on reset and when a falling edge is detected on the RESET pin. CALIBRATION ENGINE TIME ~650ns 650ns 650ns 350ns WRITE 1 FIRST STAGE SECOND STAGE THIRD STAGE FIRST STAGE SECOND STAGE THIRD STAGE FIRST STAGE SECOND STAGE THIRD STAGE WRITE 2 FIRST STAGE SECOND STAGE Table 17.
AD5522 Data Sheet REGISTER UPDATE RATES Table 19. Mode Bits The value of the X2 register is calculated each time the user writes new data to the corresponding X1 register and for some PMU register updates. The calculation is performed in a three-stage process. The first two stages take approximately 650 ns each, and the third stage takes approximately 350 ns. When the write to the X1 register is complete, the calculation process begins.
Data Sheet AD5522 All codes not explicitly referenced in this table are reserved and should not be used (see Table 29). Table 20.
AD5522 Data Sheet WRITE SYSTEM CONTROL REGISTER functions in the device. The system control register operates on a per-device basis. The system control register is accessed when the PMU channel address bits (PMU3 to PMU0) and the mode bits (MODE1 and MODE0) are all 0s. This register allows quick setup of various Table 21.
Data Sheet Bit 7 6 Bit Name GAIN1 GAIN0 5 TMP ENABLE 4 3 TMP1 TMP0 2 Latched 1 0 (LSB) 0 0 AD5522 Description MEASOUTx output range. The MEASOUTx range defaults to the force voltage span for voltage and current measurements, which includes some overrange to allow for offset correction. The nominal output voltage range is ±11.25 V with the default offset DAC setting, but changes for other offset DAC settings when GAIN1 = 0. Therefore, the MEASOUTx range can be an asymmetrical bipolar voltage range.
AD5522 Data Sheet WRITE PMU REGISTER To address PMU functions, set the MODE1 and MODE0 bits to 0. This setting selects the PMU register (see Table 19 and Table 20). The AD5522 has very flexible addressing, which allows writing of data to a single PMU channel, any combination of PMU channels, or all PMU channels. This functionality enables multipin broadcasting to similar pins on a DUT. Bit 27 to Bit 24 select the PMU or group of PMUs that is addressed. Table 24.
Data Sheet Bit 14 13 Bit Name MEAS1 MEAS0 12 FIN 11 10 SF0 SS0 9 CL 8 CPOLH 7 Compare V/I Clear 6 5 4 3 2 1 0 (LSB) Unused AD5522 Description The MEAS1 and MEAS0 bits specify the required measure mode, allowing the MEASOUTx line to be disabled, connected to the temperature sensor, or enabled for measurement of current or voltage.
AD5522 Data Sheet WRITE DAC REGISTER chip. Bit D15 to Bit D0 are the DAC data bits used when writing to these registers. The PMU address bits allow addressing of a particular DAC for any combination of PMU channels. The DAC input, gain, and offset registers are addressed through a combination of PMU bits (Bit 27 to Bit 24) and mode bits (Bit 23 and Bit 22). Bit A5 to Bit A0 address each DAC level on Table 27.
Data Sheet AD5522 DAC Addressing For the FIN and comparator (CPH and CPL) DACs, there is a set of X1, M, and C registers for each current range, and one set for the voltage range; for the clamp DACs (CLL and CLH), there are only two sets of X1, M, and C registers. When calibrating the device, the M and C registers allow volatile storage of gain and offset coefficients.
AD5522 Data Sheet A5 1 A4 0 A3 0 A2 0 A1 0 A0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 2 MODE1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 MODE0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 CLL should be within the range of 0x0000 to 0x7FFF. CLH should be within the range of 0x8000 to 0xFFFF. Rev.
Data Sheet AD5522 READ REGISTERS Readback of all the registers in the device is possible via the SPI and the LVDS interfaces. To read data from a register, it is first necessary to write a readback command to tell the device which register is required for readback. See Table 30 to address the appropriate channel. When the required channel is addressed, the device loads the 24-bit readback data into the MSB positions of the 29-bit serial shift register (the five LSBs are filled with 0s).
AD5522 Data Sheet READBACK OF SYSTEM CONTROL REGISTER The system control register readback function is a 24-bit word. Mode and system control register data bits are shown in Table 31. Table 31. System Control Register Readback Bit Bit Name Description 23 (MSB) MODE1 Set the MODE1 and MODE0 bits to 0 to address the system control register. 22 MODE0 System Control Register-Specific Readback Bits 21 CL3 Read back the status of the individual current clamp enable bits. 0 = clamp is disabled.
Data Sheet AD5522 READBACK OF PMU REGISTER The PMU register readback function is a 24-bit word that includes the mode and PMU data bits. Only one PMU register can be read back at any one time. Table 32.
AD5522 Data Sheet READBACK OF COMPARATOR STATUS REGISTER READBACK OF ALARM STATUS REGISTER The comparator status register is a read-only register that provides access to the output status of each comparator pin on the chip. Table 33 shows the format of the comparator register readback word. The alarm status register is a read-only register that provides information about temperature, clamp, and guard alarm events (see Table 34).
Data Sheet AD5522 READBACK OF DAC REGISTER The DAC register readback function is a 24-bit word that includes the mode, address, and DAC data bits. Table 35. DAC Register Readback Bit 23 (MSB) 22 Bit Name MODE1 MODE0 DAC Register-Specific Bits 21 to 16 A5 to A0 15 to 0 (LSB) D15 to D0 Description The MODE1 and MODE0 bits indicate the type of DAC register (X1, M, or C) that is read. 01 = DAC gain (M) register. 10 = DAC offset (C) register. 11 = DAC input data (X1) register.
AD5522 Data Sheet APPLICATIONS INFORMATION POWER-ON DEFAULT The power-on default for all DAC channels is that the contents of each M register are set to full scale (0xFFFF), and the contents of each C register are set to midscale (0x8000). The contents of the DAC X1 registers at power-on are listed in Table 36. The power-on default for the alarm status register is 0xFFFFF0, and the power-on default for the comparator status register is 0x400000.
Data Sheet AD5522 CHANGING MODES 3. There are different ways of handling a mode change. 2. Load any DAC X1 values that require changes. Remember that for force amplifier and comparator DACs, X1 registers are available per voltage and current range, so the user can preload new DAC values to make DAC updates ahead of time; the calibration engine calculates the X2 values and stores them. Change to the new PMU mode (FI or FV).
AD5522 Data Sheet Table 39. ADCs and ADC Drivers Suggested For Use with AD5522 1 Part No. AD7685 Resolution 16 Sample Rate 250 kSPS Ch. No.
Data Sheet AD5522 DRIVEN SHIELD DAC ADC CENTRAL PMU GUARD AMP AD5522 VCH DAC DAC TIMING DATA MEMORY TIMING GENERATOR DLL, LOGIC DAC ADC VTERM DAC DAC PMU PMU DAC DAC PMU PMU VH DUT RELAYS FORMATTER DESKEW 50Ω COAX DRIVER VL DAC DAC VCL GND SENSE DAC COMPARE MEMORY FORMATTER DESKEW VTH COMP DAC ACTIVE LOAD DAC AD5560 DEVICE POWER SUPPLY VCOM 06197-038 DAC GUARD AMP ADC IOL DAC DAC VTL IOH Figure 59.
AD5522 Data Sheet OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.20 MAX 80 61 61 1 80 1 60 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) BOTTOM VIEW 0° MIN 0.15 0.05 SEATING PLANE (PINS UP) 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 20 41 41 40 21 20 21 40 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Data Sheet AD5522 ORDERING GUIDE Model 1 AD5522JSVDZ AD5522JSVUZ EVAL-AD5522EBDZ EVAL-AD5522EBUZ 1 Temperature Range (TJ) 25°C to 90°C 25°C to 90°C Package Description 80-Lead TQFP_EP with Exposed Pad on Bottom 80-Lead TQFP_EP with Exposed Pad on Top Evaluation Board with Exposed Pad on Bottom Evaluation Board with Exposed Pad on Top Z = RoHS Compliant Part. Rev.
AD5522 Data Sheet NOTES ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06197-0-5/12(E) Rev.
