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1 MSPS, Ultralow Power,

12-Bit ADC in 10-Lead LFCSP and MSOP

Data Sheet

AD7091R

Rev. 0

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FEATURES

Fast throughput rate of 1 MSPS

Specified for V

of 2.7 V to 5.25 V

Logic voltage V

DRIVE

of 1.65 V to 5.25 V

INL of ±1 LSB maximum

Analog input range of 0 V to V

REF

Ultralow power

349 µA typical at 3 V and 1 MSPS

264 nA typical at 3 V in power-down mode

Internal 2.5 V reference, ±4.5 ppm/°C typical drift

Wide input bandwidth

Flexible power/throughput rate management

High speed serial interface

SPI®/QSPI™/MICROWIRE™/DSP compatible

BUSY indicator

Power-down mode

10-lead, 3 mm × 2 mm LFCSP and 10-lead MSOP packages

Temperature range of −40°C to +125°C

APPLICATIONS

Battery-powered systems

Handheld meters

Medical instruments

Mobile communications

Instrumentation and control systems

Data acquisition systems

Optical sensors

Diagnostic/monitoring functions

Energy harvesting

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Figure 2. Power vs. Throughput Rate

GENERAL DESCRIPTION

The AD7091R is a 12-bit successive approximation analog-to-

digital converter (ADC) that offers ultralow power consumption

(typically 349 µA at 3 V and 1 MSPS) while achieving fast

throughput rates (1 MSPS with a 50 MHz SCLK). Operating

from a single 2.7 V to 5.25 V power supply, the part contains a

wide bandwidth track-and-hold amplifier that can handle input

frequencies in excess of 7 MHz. The AD7091R also features an

on-chip conversion clock, accurate reference, and high speed

serial interface.

The conversion process and data acquisition are controlled using

CONVST

signal and an internal oscillator. The AD7091R has

a serial interface that allows data to be read after the conversion

while achieving a 1 MSPS throughput rate.

The AD7091R uses advanced design and process techniques to

achieve very low power dissipation at high throughput rates. An

on-chip, accurate 2.5 V reference is available.

PRODUCT HIGHLIGHTS

1. Lowest Power 12-Bit SAR ADC Available.

2. On-Chip, Accurate 2.5 V Reference.

3. High Throughput Rate with Ultralow Power Consumption.

4. Flexible Power/Throughput Rate Management.

Average power scales with the throughput rate. Power-down

mode allows the average power consumption to be reduced

when the device is not performing a conversion.

5. Single Supply Operation with V

DRIVE

Function.

The AD7091R operates from a single 2.7 V to 5.25 V supply.

The V

DRIVE

function allows the serial interface to connect

directly to 1.8 V to 3.3 V processors.

2.5V

REF

CONVERSION

CONTROL LOGIC

GND

CLK

OSC

REGCAP V

12-BIT

SAR

SERIAL

INTERFACE

SDO

AD7091R

SCLK

DRIVE

CONVST

T/H

REF

/REF

OUT

10494-001

100

200

300

400

500

600

700

800

900

1000

1100

0 200 400 600 800 1000

POWER (μW)

THROUGHPUT RATE (kSPS)

DRIVE

= V

DRIVE

= 3V

= V

DRIVE

= 3V

10494-002

Summary of content (21 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM REGCAP Fast throughput rate of 1 MSPS Specified for VDD of 2.7 V to 5.25 V Logic voltage VDRIVE of 1.65 V to 5.25 V INL of ±1 LSB maximum Analog input range of 0 V to VREF Ultralow power 349 µA typical at 3 V and 1 MSPS 264 nA typical at 3 V in power-down mode Internal 2.5 V reference, ±4.
PAGE 2
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PAGE 3
AD7091R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Information .................................................................... 12 Applications ....................................................................................... 1 Converter Operation.................................................................. 12 Functional Block Diagram ......................................................
PAGE 4
Data Sheet AD7091R SPECIFICATIONS VDD = 2.7 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, VREF = 2.5 V internal reference, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C, unless otherwise noted. Table 1.
PAGE 5
AD7091R Parameter POWER REQUIREMENTS VDD VDRIVE IDD Normal Mode—Static 5 Data Sheet Test Conditions/Comments Min Typ 2.7 1.65 Max Unit 5.25 5.25 V V VIN = 0 V VDD = 5.25 V VDD = 3 V 22 21.6 60 33 µA µA VDD = 5.25 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 100 kSPS 388 349 55 449 408 µA µA µA VDD = 5.25 V VDD = 5.25 V, TA = −40°C to +85°C VDD = 3 V VDD = 3 V, TA = −40°C to +85°C VIN = 0 V 0.334 0.334 0.264 0.264 4.4 1.4 4.2 1.2 µA µA µA µA VDRIVE = 5.
PAGE 6
Data Sheet AD7091R TIMING SPECIFICATIONS VDD = 2.75 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted. 1 Table 2. Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 Limit at TMIN, TMAX 50 8 7 0.4 tSCLK 3 0.
PAGE 7
AD7091R Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VDRIVE to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature ESD HBM FICDM 1 Table 4. Thermal Resistance Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to VREF + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.
PAGE 8
Data Sheet AD7091R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 REGCAP 4 AD7091R 9 SDO TOP VIEW (Not to Scale) 8 SCLK 7 CS 6 CONVST GND 5 NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED PAD TO THE SUBSTRATE, GND. 10 VDRIVE REFIN/REFOUT 2 AD7091R 9 SDO VIN 3 TOP VIEW (Not to Scale) 8 SCLK 7 CS 6 CONVST VDD 1 REGCAP 4 GND 5 Figure 3.
PAGE 9
AD7091R Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 72 –20 VDD = 2.7V VDRIVE = 3.3V TA = 25°C fIN = 10kHz –40 fSAMPLE = 1 MSPS –60 SNR = 69.32dB SINAD = 68.66dB THD = –84.42dB 70 2.7V 3.0V 5.0V 68 SNR (dB) SNR (dB) 0 –80 66 64 –100 62 –120 TA = 25°C 100 200 300 400 500 FREQUENCY (kHz) 1 Figure 8. SNR vs. Analog Input Frequency for Various Supply Voltages 1.0 0 VDD = 2.7V VDRIVE = 3.3V TA = 25°C fSAMPLE = 1 MSPS 0.6 0.2 –40 THD (dB) –30 0.0 –0.2 –50 –70 –0.
PAGE 10
Data Sheet AD7091R 2.502 72 VDD = VDRIVE = 3V 2.500 70 2.498 2.7V 3.0V 5.0V 2.496 VREF (V) SINAD (dB) 68 66 2.494 2.492 2.490 64 +25°C –40°C +85°C +125°C 2.488 62 2.486 TA = 25°C 10 100 2.484 INPUT FREQUENCY (kHz) 0 60 80 100 Figure 14. Reference Voltage Output vs. Current Load for Various Temperatures 450 60 53423 50 VDD = VDRIVE = 3V 65k SAMPLES TA = 25°C 430 fSAMPLE = 1MSPS 410 40 30 20 390 370 350 330 310 290 10 6458 5655 2047 2048 2049 250 2.
PAGE 11
AD7091R Data Sheet 4000 3500 VDD = 3V, VDRIVE = 3V VDD = 5V, VDRIVE = 5V VDD = 5V, VDRIVE = 3.3V TOTAL CURRENT (nA) 3000 2500 2000 1500 1000 0 –40 25 85 OPERATING TEMPERATURE (°C) 125 10494-032 500 Figure 17. Total Power-Down Supply Current (IDD and IDRIVE) vs. Temperature for Various Supply Voltages Rev.
PAGE 12
Data Sheet AD7091R TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7091R, the endpoints of the transfer function are zero scale (a point 0.5 LSB below the first code transition) and full scale (a point 0.5 LSB above the last code transition). Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
PAGE 13
AD7091R Data Sheet THEORY OF OPERATION CIRCUIT INFORMATION SAMPLING CAPACITOR ACQUISITION PHASE CONTROL LOGIC SW2 COMPARATOR GND LDO/2 10494-017 SW1 B CONTROL LOGIC SW2 COMPARATOR Figure 19. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding of the AD7091R is straight binary. The designed code transitions occur midway between successive integer LSB values, such as 0.5 LSB, 1.5 LSB, and so on. The LSB size for the AD7091R is VREF/4096.
PAGE 14
Data Sheet AD7091R TYPICAL CONNECTION DIAGRAM analog input signal never exceeds VREF or VDD by more than 300 mV. These diodes can conduct a maximum of 10 mA without causing irreversible damage to the part. A positive power supply in the range of 2.7 V to 5.25 V should be connected to the VDD pin, with typical values for decoupling capacitors being 100 nF and 10 µF. These capacitors should be placed as close as possible to the device pins.
PAGE 15
AD7091R Data Sheet MODES OF OPERATION The mode of operation of the AD7091R is selected by controlling the logic state of the CONVST signal when a conversion is complete. The logic level of the CONVST pin at the end of a conversion determines whether the AD7091R remains in normal mode or enters power-down mode (see the Normal Mode and PowerDown Mode sections). Similarly, if the device is already in power-down mode, CONVST controls whether the device returns to normal mode or remains in power-down mode.
PAGE 16
Data Sheet AD7091R Normal and Power-Down Mode Combination VDRIVE supply. Power consumption for the VDRIVE supply can be calculated by the same principles as those for the VDD supply. The internal circuitry of the AD7091R requires 100 μs to power up from power-down mode. Power-down mode can therefore be performed at sampling rates of less than 10 kSPS.
PAGE 17
AD7091R Data Sheet SERIAL INTERFACE the AD7091R to enter power-down mode, CONVST should be taken high before the end of the conversion. A conversion requires 650 ns to complete. When the conversion process is finished, the track-and-hold goes back to track mode. Before the end of a conversion, pull CS low to enable the BUSY indicator feature. The AD7091R serial interface consists of four signals: SDO, SCLK, CONVST, and CS.
PAGE 18
Data Sheet AD7091R WITHOUT BUSY INDICATOR The data is shifted out of the device as a 12-bit word under the control of SCLK and CS. The MSB (Bit DB11) is clocked out on the falling edge of CS. DB10 to DB0 are shifted out on the subsequent falling edges of SCLK. The 12th falling SCLK edge returns SDO to a high impedance state. After all the data is clocked out, pull CS high again. SCLK should idle low in this mode to ensure that the MSB is not lost.
PAGE 19
AD7091R Data Sheet SOFTWARE RESET INTERFACING WITH 8-/16-BIT SPI The AD7091R requires the user to initiate a software reset when power is first applied. It should be noted that failure to apply the correct software reset command may result in a device malfunction. It is also possible to interface the AD7091R with a conventional 8-/16-bit SPI bus.
PAGE 20
Data Sheet AD7091R EOC/ SOFTWARE RESET EOC t7 t7 CONVST t8 t8 t12 CS t10 SHORT CYCLE READ SDO t3 SCLK 1 2 6 7 8 t5 10494-030 NOTES 1. DON’T CARE. 2. EOC IS THE END OF A CONVERSION. Figure 31. Software Reset Timing Rev.
PAGE 21
AD7091R Data Sheet OUTLINE DIMENSIONS 2.54 2.44 2.34 3.10 3.00 2.90 2.10 2.00 1.90 PIN 1 INDEX AREA 1.00 0.90 0.80 EXPOSED PAD 0.35 0.30 0.25 5 1 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.203 REF 05-06-2010-B 0.80 0.75 0.70 SEATING PLANE 0.50 BSC 10 6 COMPLIANT TO JEDEC STANDARDS MO-229-WCED-3 Figure 32.