User manual

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For current information contact Analog Devices at [phone]
ADSP-2192 October 2000
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
36 REV. PrA
Additional Information
This data sheet provides a general overview of the
ADSP-2192 architecture and functionality. For detailed
information on the ADSP-219x Family core architecture
and instruction set, refer to the ADSP-219x/2191 DSP
Hardware Reference.
PIN DESCRIPTIONS
ADSP-2192 pin definitions are listed in a series of tables
following this section. Inputs identified as synchronous (S)
must meet timing requirements with respect to CLKIN (or
with respect to TCK for TMS, TDI). Inputs identified as
asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST
).
The following symbols appear in the Type columns of these
tables: G = Ground, I = Input, O = Output, P = Power
Supply, and T = Three-State.
Figure 11. JTAG Scan Path Connections for Multiple ADSP-2192 Systems
ADSP-2192
P0
JTAG
DEVICE
(OPTI ONAL)
ADSP-2192
P1
TDI
EZ-ICE
JTAG
CONNECTOR
OTHER
JTAG
CONTROLLER
OPTIONAL
EMU
TMS
TCK
TDO
CLKI N
TRST
TDI TDO TDI TDO TDOTDI
TMS
TCK
TRST
TMS
TCK
TMS
TCK
EMU
TRST
EMU
TRST
Table 28. ADSP-2192 Pin Configurations: PCI/USB Bus Interface
Pin Name LQFP I/O Description
AD0 57 I/O Address and Data Bus
AD1 56 I/O Address and Data Bus
AD2 55 I/O Address and Data Bus
AD3 54 I/O Address and Data Bus
AD4 53 I/O Address and Data Bus
AD5 48 I/O Address and Data Bus
AD6 47 I/O Address and Data Bus
AD7 46 I/O Address and Data Bus
AD8 44 I/O Address and Data Bus
AD9 43 I/O Address and Data Bus
AD10 42 I/O Address and Data Bus
AD11 37 I/O Address and Data Bus