Datasheet

Ultraprecision Operational Amplifier
Data Sheet
OP177
Rev. H Document Feedback
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FEATURES
Ultralow offset voltage
T
A
= 25°C, 25 μV maximum
Outstanding offset voltage drift 0.3 μV/°C maximum
Excellent open-loop gain and gain linearity
12 V/μV typical
CMRR: 130 dB minimum
PSRR: 115 dB minimum
Low supply current 2.0 mA maximum
Fits industry-standard precision operational amplifier
sockets
PIN CONFIGURATION
8
7
6
5
1
2
3
4
NC = NO CONNECT
–IN
+IN
V+
OUT
NCV–
V
OS
TRIM V
OS
TRIM
00289-001
OP177
TOP VIEW
(Not to Scale)
Figure 1. 8-Lead PDIP (P-Suffix),
8-Lead SOIC (S-Suffix)
GENERAL DESCRIPTION
The OP177 features one of the highest precision performance of
any operational amplifier currently available. Offset voltage of the
OP177 is only 25 μV maximum at room temperature. The ultralow
V
OS
of the OP177 combines with the exceptional offset voltage
drift (TCV
OS
) of 0.3 μV/°C maximum to eliminate the need for
external V
OS
adjustment and increases system accuracy over
temperature.
The OP177 open-loop gain of 12 V/μV is maintained over the full
±10 V output range. CMRR of 130 dB minimum, PSRR of 120 dB
minimum, and maximum supply current of 2 mA are just a few
examples of the excellent performance of this operational amplifier.
The combination of outstanding specifications of the OP177
ensures accurate performance in high closed-loop gain
applications.
This low noise, bipolar input operational amplifier is also a cost
effective alternative to chopper-stabilized amplifiers. The OP177
provides chopper-type performance without the usual problems
of high noise, low frequency chopper spikes, large physical size,
limited common-mode input voltage range, and bulky external
storage capacitors.
The OP177 is offered in the 40°C to +85°C extended industrial
temperature ranges. This product is available in 8-lead PDIP, as
well as the space saving 8-lead SOIC.
FUNCTIONAL BLOCK DIAGRAM
2B
C
1
R
7
(OPTIONAL NULL)
Q
19
R
2B
*R
2A
*
R
1B
R
1A
R
9
R
10
OUTPUT
R
8
R
6
C
3
C
2
Q
13
Q
17
R
5
Q
27
Q
26
Q
25
Q
8
Q
7
Q
23
Q
24
Q
21
Q
22
Q
9
Q
4
Q
6
Q
3
Q
5
R
3
R
4
Q
1
Q
2
Q
11
Q
12
Q
14
Q
10
Q
16
Q
15
Q
18
Q
20
V+
V–
NONINVERTING
INPUT
INVERTING
INPUT
*R
2A
AND R
2B
ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
00289-002
Figure 2. Simplified Schematic

Summary of content (16 pages)