Datasheet

Data Sheet REF19x Series
Rev. L | Page 23 of 28
Although this concept is simple, some cautions are needed. Because
the lower reference circuit must sink a small bias current from U2
(50 μA to 100 μA), plus the base current from the series PNP output
transistor in U2, either the external load of U1 or R1 must provide
a path for this current. If the U1 minimum load is not well defined,
Resistor R1 should be used, set to a value that conservatively passes
600 μA of current with the applicable V
OUT1
across it. Note that the
two U1 and U2 reference circuits are locally treated as macrocells,
each having its own bypasses at input and output for best stability.
Both U1 and U2 in this circuit can source dc currents up to
their full rating. The minimum input voltage, V
S
, is determined by
the sum of the outputs, V
OUT2
, plus the dropout voltage of U2.
A related variation on stacking two 3-terminal references is shown
in Figure 28, where U1, a REF192, is stacked with a 2-terminal
reference diode, such as the AD589. Like the 3-terminal stacked
reference shown in Figure 27, this circuit provides two outputs,
V
OUT1
and V
OUT2
, which are the individual terminal voltages of D1
and U1, respectively. Here this is 1.235 V and 2.5 V, which provides a
V
OUT2
of 3.735 V. When using 2-terminal reference diodes, such as
D1, the rated minimum and maximum device currents must be
observed, and the maximum load current from V
OUT1
can be no
greater than the current setup by R1 and V
O
(U1). When V
O
(U1) is equal to 2.5 V, R1 provides a 500 μA bias to D1, so the
maximum load current available at V
OUT1
is 450 μA or less.
D1
AD589
R1
4.99kΩ
(SEE TEXT)
C1
0.1μF
+V
S
V
S
> V
OUT2
+ 0.15V
V
IN
COMMON
V
OUT
COMMON
+V
OUT2
3.735V
C2
1μF
+V
OUT1
1.235V
C3
1μF
U1
REF192
2
63
4
+
+
V
O
(U1)
V
O
(D1)
00371-026
Figure 28. Stacking Voltage References with the REF192
PRECISION CURRENT SOURCE
In low power applications, the need often arises for a precision
current source that can operate on low supply voltages. As
shown in Figure 29, any one of the devices in the REF19x family
of references can be configured as a precision current source.
The circuit configuration illustrated is a floating current source
with a grounded load. The output voltage of the reference is
bootstrapped across R
SET
, which sets the output current into the
load. With this configuration, circuit precision is maintained for
load currents in the range from the reference’s supply current
(typically 30 μA) to approximately 30 mA. The low dropout
voltage of these devices maximizes the current source’s output
voltage compliance without excess headroom.
I
SY
ADJUST
R1
R
SET
P1
R
L
I
OUT
FOR EXAMPLE, REF195: V
OUT
= 5V
I
OUT
= 5mA
R1 = 953Ω
P1 = 100Ω, 10-TURN
V
S
1µF
REF19x
2
3
4
6
V
IN
≥ I
OUT
× R
L
(MAX) + V
SY
(MIN)
I
OUT
=
V
OUT
+ I
SY
(REF19x)
R
SET
V
OUT
>> I
SY
R
SET
V
S
GND
OUTPUTSLEEP
00371-027
Figure 29. A Low Dropout, Precision Current Source
SWITCHED OUTPUT 5 V/3.3 V REFERENCE
Applications often require digital control of reference voltages,
selecting between one stable voltage and a second. With the
sleep feature inherent to the REF19x series, switched output
reference configurations are easily implemented with little
additional hardware.
The circuit in Figure 30 shows the general technique, which takes
advantage of the output wire-OR capability of the REF19x device
family. When off, a REF19x device is effectively an open circuit
at the output node with respect to the power supply. When on, a
REF19x device can source current up to its current rating, but
sink only a few μA (essentially, just the relatively low current of the
internal output scaling divider). Consequently, when two devices
are wired together at their common outputs, the output voltage
is the same as the output voltage for the on device. The off state
device draws a small standby current of 15 μA (maximum), but
otherwise does not interfere with operation of the on device, which
can operate to its full current rating. Note that the two devices in
the circuit conveniently share both input and output capacitors,
and with CMOS logic drive, it is power efficient.
U3B
74HC04
U3A
74HC04
V
C
V
OUT
(V)
5.0
3.3
4.5
5.0
V
C
*
HIGH
LOW
HIGH
LOW
U1/U2
REF195/
REF196
REF194/
REF195
*
CMOS LOGIC LEVELS
+V
S
= 6V
V
IN
COMMON
V
OUT
COMMON
C1
0.1µF
+V
OUT
C2
1µF
U1
REF19x
(SEE TABLE)
2
3
4
U2
REF19x
(SEE TABLE)
2
3
4
+
6
6
1324
OUTPUT T
A
BLE
00371-028
Figure 30. Switched Output Reference