Datasheet

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Low Power Audio Codec

Data Sheet

SSM2603

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FEATURES

Stereo, 24-bit analog-to-digital and digital-to-analog converters

DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V

ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V

Highly efficient headphone amplifier

Stereo line input and monaural microphone input

Low power

7 mW stereo playback (1.8 V/1.5 V supplies)

14 mW record and playback (1.8 V/1.5 V supplies)

Low supply voltages

Analog: 1.8 V to 3.6 V

Digital core: 1.5 V to 3.6 V

Digital I/O: 1.8 V to 3.6 V

256/384 oversampling rate in normal mode; 250/272 over-

sampling rate in USB mode

Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,

and 96 kHz

28-lead, 5 mm × 5 mm LFCSP (QFN) package

APPLICATIONS

Mobile phones

MP3 players

Portable gaming

Portable electronics

Educational toys

GENERAL DESCRIPTION

The SSM2603 is a low power, high quality stereo audio codec

for portable digital audio applications with one set of stereo

programmable gain amplifier (PGA) line inputs and one

monaural microphone input. It features two 24-bit analog-to-

digital converter (ADC) channels and two 24-bit digital-to-

analog (DAC) converter channels.

The SSM2603 can operate as a master or a slave. It supports

various master clock frequencies, including 12 MHz or 24 MHz

for USB devices; standard 256 f

or 384 f

based rates, such as

12.288 MHz and 24.576 MHz; and many common audio sampling

rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24

kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.

The SSM2603 can operate at power supplies as low as 1.8 V for

the analog circuitry and as low as 1.5 V for the digital circuitry.

The maximum voltage supply is 3.6 V for all supplies.

The SSM2603 software-programmable stereo output options

provide the user with many application possibilities. Its volume

control functions provide a large range of gain control of the

audio signal.

The SSM2603 is specified over the industrial temperature range

of −40°C to +85°C. It is available in a 28-lead, 5 mm × 5 mm

lead frame chip scale package (LFCSP).

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

AVDD VMID AGND DBVDD DGND DCVDD HPVDD PGND

MICBIAS

RHPOUT

ROUT

MICIN

DIGITAL

PROCESSOR

RLINEIN

MUX

ADC

LLINEIN

MUX

ADC

DAC

LOUT

LHPOUT

SIDETONE

BYPASS

SIDETONE

BYPASS

CLK

MCLK/

XTI

XTO

CLKOUT

CONTROL INTERFACE

MUTE CSB

SDIN SCLK

DIGITAL AUDIO INTERFACE

PBDAT RECDAT

BCLK PBLRC

RECLRC

0dB/20dB BOOST

–34.5dB TO +33dB,

1.5dB STEP

–34.5dB TO +33dB,

1.5dB STEP

–73dB TO +6dB,

1dB STEP

–73dB TO +6dB,

1dB STEP

–6dB TO –15dB/MUTE –3dB STEP

07241-001

SSM2603

Summary of content (32 pages)

PAGE 1
Low Power Audio Codec SSM2603 Data Sheet FEATURES GENERAL DESCRIPTION Stereo, 24-bit analog-to-digital and digital-to-analog converters DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V Highly efficient headphone amplifier Stereo line input and monaural microphone input Low power 7 mW stereo playback (1.8 V/1.5 V supplies) 14 mW record and playback (1.8 V/1.5 V supplies) Low supply voltages Analog: 1.8 V to 3.6 V Digital core: 1.5 V to 3.
PAGE 2
SSM2603 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Audio Interface .............................................................. 15 Applications ....................................................................................... 1 Software Control Interface ........................................................ 17 General Description ...............................................................
PAGE 3
Data Sheet SSM2603 SPECIFICATIONS TA = 25°C, AVDD = DVDD = 3.3 V, HPVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted. Table 1. Parameter RECOMMENDED OPERATING CONDITIONS Analog Voltage Supply (AVDD) Digital Core Power Supply Digital I/O Supply Ground (AGND, PGND, DGND) POWER CONSUMPTION Power-Up Stereo Record (1.5 V and 1.8 V) Stereo Record (3.3 V) Stereo Playback (1.5 V and 1.8 V) Stereo Playback (3.
PAGE 4
SSM2603 Data Sheet Parameter HEADPHONE OUTPUT Full-Scale Output Voltage Maximum Output Power Min Signal-to-Noise Ratio (A-Weighted) 85 THD + N Power Supply Rejection Ratio Mute Attenuation LINE INPUT TO LINE OUTPUT Full-Scale Output Voltage Signal-to-Noise Ratio (A-Weighted) THD + N Power Supply Rejection MICROPHONE INPUT TO HEADPHONE OUTPUT Full-Scale Output Voltage Signal-to-Noise Ratio (A-Weighted) Power Supply Rejection Ratio Programmable Attenuation Gain Step Mute Attenuation 1 Typ Max Unit 1
PAGE 5
Data Sheet SSM2603 TIMING CHARACTERISTICS Table 3. I2C® Timing tMIN 600 600 600 1.
PAGE 6
SSM2603 Data Sheet Table 5.
PAGE 7
Data Sheet SSM2603 ABSOLUTE MAXIMUM RATINGS At 25°C, unless otherwise noted. THERMAL RESISTANCE Table 7. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5V VDD VDD −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C Table 8.
PAGE 8
SSM2603 Data Sheet 28 27 26 25 24 23 22 SCLK SDIN CSB MUTE LLINEIN RLINEIN MICIN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 PIN 1 INDICATOR SSM2603 TOP VIEW (Not to Scale) 21 20 19 18 17 16 15 MICBIAS VMID AGND AVDD ROUT LOUT PGND NOTES 1. CONNECT THE EXPOSED PAD TO THE PCB GROUND LAYER. 07241-002 PBDAT PBLRC RECDAT RECLRC HPVDD LHPOUT RHPOUT 8 9 10 11 12 13 14 MCLK/XTI XTO DCVDD DGND DBVDD CLKOUT BCLK Figure 6. Pin Configuration Table 9. Pin Function Descriptions Pin No.
PAGE 9
Data Sheet SSM2603 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –100 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 FREQUENCY (fS) 0 0.03 0.03 0.02 0.02 MAGNITUDE (dB) 0.04 0.01 0 −0.01 −0.02 0.25 0.30 0.35 FREQUENCY (fS) 0.40 0.45 1.75 2.00 −0.02 −0.04 0.20 1.50 −0.01 −0.04 0.15 1.25 0 −0.03 0.10 1.00 0.01 −0.03 0.50 07241-004 MAGNITUDE (dB) 0.05 0.04 0.05 0.75 Figure 9.
PAGE 10
SSM2603 Data Sheet DIGITAL DE-EMPHASIS 0 0.4 −1 0.3 −2 0.2 MAGNITUDE (dB) −4 −5 −6 −7 0 −0.1 −0.2 −8 −0.3 −9 0 4 8 12 16 FREQUENCY (kHz) −0.4 07241-007 −10 0.1 0 4 8 12 16 07241-010 MAGNITUDE (dB) −3 20 FREQUENCY (kHz) Figure 14. De-Emphasis Error, Audio Sampling Rate = 44.1 kHz Figure 11. De-Emphasis Frequency Response, Audio Sampling Rate = 32 kHz 0 0.4 −1 0.3 −2 −3 MAGNITUDE (dB) 0.1 0 −0.1 −0.
PAGE 11
Data Sheet SSM2603 THEORY OF OPERATION DIGITAL CORE CLOCK Inside the SSM2603 digital core is one central clock source, called the core clock, that produces a reference clock for all internal audio data processing and synchronization. When using an external clock source to drive the MCLK pin, great care should be taken to select a clock source with less than 50 ps of jitter. Without careful generation of the MCLK signal, the digital audio quality may suffer.
PAGE 12
SSM2603 Data Sheet AUTOMATIC LEVEL CONTROL (ALC) Attack (Gain Ramp-Down) Time The SSM2603 codec has an automatic level control (ALC) that can be activated to suppress clipping and improve dynamic range even if a sudden, loud input signal is introduced. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. Attack time is the time taken for the PGA gain to ramp down through 90% of its range.
PAGE 13
Data Sheet SSM2603 ANALOG INTERFACE GAIN = The SSM2603 includes stereo single-ended line and monaural microphone inputs to the on-board ADC. Either the line inputs or the microphone input, but not both simultaneously, can be connected to the ADC by setting the INSEL bit (Register R4, Bit D2). In addition, the line or microphone inputs can be routed and mixed directly to the output terminals via the SIDETONE_EN (Register R4, Bit D5) and BYPASS (Register R4, Bit D3) bits.
PAGE 14
SSM2603 Data Sheet The line and microphone inputs can be routed and mixed directly to the output terminals via the SIDETONE_EN (Register R4, Bit D5) and bypass (Register R4, Bit D3) software control register selections. In both of these modes, the analog input signal is routed directly to the output terminals and is not digitally converted. The bypass signal at the output mixer is the same level as the output of the PGA associated with each line input.
PAGE 15
Data Sheet SSM2603 DIGITAL AUDIO INTERFACE Digital Audio Data Sampling Rate The digital audio input can support the following four digital audio communication protocols: right-justified mode, left-justified mode, I2S mode, and digital signal processor (DSP) mode. To accommodate a wide variety of commonly used DAC and ADC sampling rates, the SSM2603 allows for two modes of operation, normal and USB, selected by the USB bit (Register R8, Bit D0).
PAGE 16
SSM2603 Data Sheet 1/fS LEFT CHANNEL RIGHT CHANNEL RECLRC/ PBLRC BCLK X X N 4 3 2 1 X X N 4 3 2 1 N X 07241-014 RECDAT/ PBDAT X = DON’T CARE. Figure 24. Right-Justified Audio Input Mode 1/fS LEFT CHANNEL RIGHT CHANNEL RECLRC/ PBLRC BCLK X 1 2 3 4 N X X 1 2 3 07241-015 RECDAT/ PBDAT X = DON’T CARE. Figure 25. I2S Audio Input Mode 1/fS LEFT CHANNEL RIGHT CHANNEL RECLRC/ PBLRC BCLK 1 2 3 N 1 2 3 N X X X 07241-016 RECDAT/ PBDAT X = DON’T CARE.
PAGE 17
Data Sheet SSM2603 SOFTWARE CONTROL INTERFACE CONTROL REGISTER SEQUENCING The software control interface provides access to the user-selectable control registers and can operate with a 2-wire (I2C) interface. 1. Within each control register is a control data-word consisting of 16 bits, MSB first. Bit B15 to Bit B9 are the register map address, and Bit B8 to Bit B0 are register data for the associated register map.
PAGE 18
SSM2603 Data Sheet TYPICAL APPLICATION CIRCUITS AVDD VMID AGND DBVDD DGND DCVDD HPVDD PGND SSM2603 PWROFF REF BYPASS MICBIAS SIDETONE ADC RLINEIN MUX DAC ADC RHPOUT DAC ROUT DIGITAL PROCESSOR MICIN OUT MIC LOUT ADC MUX LLINEIN DAC LHPOUT LINE SIDETONE BYPASS CLKOUT OSC MCLK/XTI CLK GEN XTO CLKOUT DIGITAL AUDIO INTERFACE CONTROL INTERFACE PBDAT RECDAT BCLK PBLRC RECLRC MUTE CSB 07241-020 OSC SDIN SCLK Figure 30.
PAGE 19
Data Sheet SSM2603 REGISTER MAP Table 10. Register Map Reg.
PAGE 20
SSM2603 Data Sheet REGISTER MAP DETAILS LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00 Table 11. Left-Channel ADC Input Volume Register Bit Map D8 LRINBOTH D7 LINMUTE D6 0 D5 D4 D3 D2 LINVOL[5:0] D1 D0 Table 12.
PAGE 21
Data Sheet SSM2603 RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01 Table 13. Right-Channel ADC Input Volume Register Bit Map D8 RLINBOTH D7 RINMUTE D6 0 D5 D4 D3 D2 RINVOL[5:0] D1 D0 Table 14.
PAGE 22
SSM2603 Data Sheet LEFT-CHANNEL DAC VOLUME, ADDRESS 0x02 Table 15. Left-Channel DAC Volume Register Bit Map D8 LRHPBOTH D7 0 D6 D5 D4 D3 D2 LHPVOL[6:0] D1 D0 Table 16.
PAGE 23
Data Sheet SSM2603 ANALOG AUDIO PATH, ADDRESS 0x04 Table 19. Analog Audio Path Register Bit Map D8 0 D7 D6 SIDETONE_ATT[1:0] D5 SIDETONE_EN D4 DACSEL D3 Bypass D2 INSEL D1 MUTEMIC D0 MICBOOST Table 20. Descriptions of Analog Audio Path Register Bits Bit Name SIDETONE_ATT[1:0] Description Microphone sidetone gain control. SIDETONE_EN Sidetone enable. Allows attenuated microphone signal to be mixed at device output terminal. DACSEL DAC select.
PAGE 24
SSM2603 Data Sheet POWER MANAGEMENT, ADDRESS 0x06 Table 23. Power Management Register Bit Map D8 0 D7 PWROFF D6 CLKOUT D5 OSC D4 Out D3 DAC D2 ADC D1 MIC D0 LINEIN Table 24.
PAGE 25
Data Sheet SSM2603 DIGITAL AUDIO I/F, ADDRESS 0x07 Table 26. Digital Audio I/F Register Bit Map D8 0 D7 BCLKINV D6 MS D5 LRSWAP D4 LRP D3 D2 WL[1:0] D1 D0 Format[1:0] Table 27.
PAGE 26
SSM2603 Data Sheet Table 30. Sampling Rate Lookup Table, USB Disabled (Normal Mode) MCLK (CLKDIV2 = 0) 12.288 MHz MCLK (CLKDIV2 = 1) 24.576 MHz 11.2896 MHz 22.5792 MHz 18.432 MHz 36.864 MHz 16.9344 MHz 33.8688 MHz 1 ADC Sampling Rate (RECLRC) 8 kHz (MCLK/1536) 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 8.0182 kHz (MCLK/1408) 11.025 kHz (MCLK/1024) 22.05 kHz (MCLK/512) 44.
PAGE 27
Data Sheet SSM2603 Table 31. Sampling Rate Lookup Table, USB Enabled (USB Mode) MCLK (CLKDIV2 = 0) 12.000 MHz 1 MCLK (CLKDIV2 = 1) 24.000 MHz ADC Sampling Rate (RECLRC) 8 kHz (MCLK/1500) 8 kHz (MCLK/1500) 8.0214 kHz (MCLK/1496) 8.0214 kHz (MCLK/1496) 11.0259 kHz (MCLK/1088) 12 kHz (MCLK/1000) 16 kHz (MCLK/750) 22.0588 kHz (MCLK/544) 24 kHz (MCLK/500) 32 kHz (MCLK/375) 44.118 kHz (MCLK/272) 44.118 kHz (MCLK/272) 48 kHz (MCLK/250) 48 kHz (MCLK/250) 88.
PAGE 28
SSM2603 Data Sheet ACTIVE, ADDRESS 0x09 Table 32. Active Register Bit Map D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 Active Table 33. Descriptions of Active Register Bit Bit Name Active Description Digital core activation control Settings 0 = disable digital core (default) 1 = activate digital core SOFTWARE RESET, ADDRESS 0x0F Table 34. Software Reset Register Bit Map D8 D7 D6 D5 D4 D3 D2 D1 D0 Reset[8:0] Table 35.
PAGE 29
Data Sheet SSM2603 ALC CONTROL 1, ADDRESS 0x10 Table 36. ALC Control 1 Register Bit Map D8 D7 ALCSEL[1:0] D6 D5 D4 MAXGAIN[2:0] D3 D2 D1 ALCL[3:0] D0 Table 37.
PAGE 30
SSM2603 Data Sheet NOISE GATE, ADDRESS 0x12 Table 40. Noise Gate Register Bit Map D8 0 D7 D6 D5 NGTH[4:0] D4 D3 D2 D1 NGG[1:0] Table 41. Descriptions of Noise Gate Register Bits Bit Name NGTH[4:0] Description Noise gate threshold NGG[1:0] Noise gate type NGAT Noise gate control 1 Settings 00000 = −76.5 dBFS (default) 00001 = −75 dBFS … In 1.5 dBFS steps 11110 = −31.
PAGE 31
Data Sheet SSM2603 OUTLINE DIMENSIONS 22 0.50 BSC 1 21 EXPOSED PAD 3.40 3.30 SQ 3.20 15 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 7 14 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE PIN 1 INDICATOR 28 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-3. 05-23-2012-B PIN 1 INDICATOR 0.30 0.25 0.18 5.10 5.00 SQ 4.90 Figure 32.