Datasheet

Data Sheet SSM2603
Rev. C | Page 17 of 32
SOFTWARE CONTROL INTERFACE
The software control interface provides access to the user-selectable
control registers and can operate with a 2-wire (I
2
C) interface.
Within each control register is a control data-word consisting of
16 bits, MSB first. Bit B15 to Bit B9 are the register map address,
and Bit B8 to Bit B0 are register data for the associated register map.
SDIN generates the serial control data-word, SCLK clocks the
serial data, and CSB determines the I
2
C device address. If the
CSB pin is set to 0, the address selected is 0011010; if 1, the
address is 0011011.
CONTROL REGISTER SEQUENCING
1. Enable all of the necessary power management bits of
Register R6 with the exception of the out bit (Bit D4). The
out bit should be set to 1 until the final step of the control
register sequence.
2. After the power management bits are set, program all other
necessary registers, with the exception of the active bit
[Register R9, Bit D0] and the out bit of the power manage-
ment register.
3. As described in the Digital Core Clock section of the
Theory of Operation, insert enough delay time to charge
the VMID decoupling capacitor before setting the active
bit [Register R9, Bit D0] .
4. Finally, to enable the DAC output path of the SSM2603, set
the out bit of Register R6 to 0.
Figure 28. 2-Wire I
2
C Generalized Clocking Diagram
Figure 29. I
2
C Write and Read Sequences
07241-019
P
98
1 TO 7
98
1 TO 7
98
1 TO 7
S
SDIN
SCLK
START ADDR R/W
ACK ACKSUBADDRESS ACK STOPDATA
07241-022
WRITE
SEQUENCE
READ
SEQUENCE
S A1A7 A0 A(S) A(S) SB15 B9 0
0 1
0 P
0... A1A7 A0 A(S)... B0 B8B7 A(M) A(M)...
B0B7 P...
......
DEVICE
ADDRESS
DEVICE
ADDRESS
REGISTER
ADDRESS
S A1A7 A0 A(S) A(S) A(S)B15 B9 B8
0
... ...
DEVICE
ADDRESS
REGISTER
ADDRESS
REGISTER
DATA
(SLAVE DRIVE)
REGISTER
DATA
S/P = START/STOP BIT.
A0 = I
2
C R/W BIT.
A(S) = ACKNOWLEDGE BY SLAVE.
A(M) = ACKNOWLEDGE BY MASTER.
A(M) = ACKNOWLEDGE BY MASTER (INVERSION).