Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsSSM2604CPZ-REEL7

Low Power Audio Codec

Data Sheet

SSM2604

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Stereo, 24-bit analog-to-digital and digital-to-analog converters

DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V

ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V

Stereo line inputs

Low power

7 mW stereo playback (1.8 V/1.5 V supplies)

14 mW record and playback (1.8 V/1.5 V supplies)

Low supply voltages

Analog: 1.8 V to 3.6 V

Digital: 1.5 V to 3.6 V

256/384 oversampling rate in normal mode;

250/272 oversampling rate in USB mode

Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,

and 96 kHz

20-lead, 4 mm × 4 mm LFCSP (QFN) package

APPLICATIONS

Mobile phones

MP3 players

Portable gaming

Portable electronics

Educational toys

GENERAL DESCRIPTION

The SSM2604 is a low power, high quality stereo audio codec

for portable digital audio applications with one set of stereo

programmable gain amplifier (PGA) line inputs. It features two

24-bit analog-to-digital converter (ADC) channels and two

24-bit digital-to-analog (DAC) converter channels.

The SSM2604 can operate as a master or a slave. It supports

various master clock frequencies, including 12 MHz or 24 MHz

for USB devices; standard 256 f

or 384 f

based rates, such as

12.288 MHz and 24.576 MHz; and many common audio sam-

pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz,

24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.

The SSM2604 can operate at power supplies as low as 1.8 V for

the analog circuitry and as low as 1.5 V for the digital circuitry.

The maximum voltage supply is 3.6 V for all supplies.

The SSM2604 is specified over the industrial temperature range

of −40°C to +85°C. It is available in a 20-lead, 4 mm × 4 mm

lead frame chip scale package (LFCSP).

FUNCTIONAL BLOCK DIAGRAM

AVDD

VMID AGND DVDD DGND

ROUT

DIGITAL

PROCESSOR

RLINEIN

ADC

LLINEIN

ADC

DAC

LOUT

BYPASS

CLK

MCLK/

XTI

XTO CLKOUT

CONTROL INTERFACE

SDIN SCLK

DIGITAL AUDIO INTERFACE

PBDAT RECDAT BCLK PBLRC RECLRC

–34.5dB TO +33dB,

1.5dB STEP

–34.5dB TO +33dB,

1.5dB STEP

SSM2604

06978-001

Figure 1.

Summary of content (28 pages)

PAGE 1
Low Power Audio Codec SSM2604 Data Sheet FEATURES GENERAL DESCRIPTION Stereo, 24-bit analog-to-digital and digital-to-analog converters DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V Stereo line inputs Low power 7 mW stereo playback (1.8 V/1.5 V supplies) 14 mW record and playback (1.8 V/1.5 V supplies) Low supply voltages Analog: 1.8 V to 3.6 V Digital: 1.5 V to 3.
PAGE 2
SSM2604 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Interface ......................................................................... 12 Applications ....................................................................................... 1 Digital Audio Interface .............................................................. 12 General Description ........................................................
PAGE 3
Data Sheet SSM2604 SPECIFICATIONS TA = 25°C, AVDD = DVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted. Table 1. Parameter RECOMMENDED OPERATING CONDITIONS Analog Voltage Supply (AVDD) Digital Power Supply Ground (AGND, DGND) POWER CONSUMPTION Power-Up Stereo Record (1.5 V and 1.8 V) Stereo Record (3.3 V) Stereo Playback (1.5 V and 1.8 V) Stereo Playback (3.
PAGE 4
SSM2604 Data Sheet DIGITAL FILTER CHARACTERISTICS Table 2. Parameter ADC FILTER Pass Band Min Typ 0 Max Unit Conditions 0.445 fS Hz Hz dB Hz dB Hz Hz Hz ±0.04 dB −6 dB 0.5 fS Pass-Band Ripple Stop Band Stop-Band Attenuation High-Pass Filter Corner Frequency DAC FILTER Pass Band ±0.04 0.555 fS −61 3.7 10.4 21.6 0 0.445 fS 0.5 fS Pass-Band Ripple Stop Band Stop-Band Attenuation CORE CLOCK TOLERANCE Frequency Range Jitter Tolerance ±0.04 0.555 fS −61 8.0 13.8 50 Rev.
PAGE 5
Data Sheet SSM2604 TIMING CHARACTERISTICS Table 3. I2C Timing Limit tMAX tMIN 600 600 600 1.
PAGE 6
SSM2604 Data Sheet Table 5.
PAGE 7
Data Sheet SSM2604 ABSOLUTE MAXIMUM RATINGS At 25°C, unless otherwise noted. THERMAL RESISTANCE Table 7. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating 3.6 V VDD VDD −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C Table 8.
PAGE 8
SSM2604 Data Sheet 20 19 18 17 16 NC SCLK SDIN LLINEIN RLINEIN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 PIN 1 INDICATOR SSM2604 TOP VIEW (Not to Scale) 15 14 13 12 11 VMID AGND AVDD ROUT LOUT NOTES 1. NC = NO CONNECT. 2. FOR PROPER CONNECTION OF THE EXPOSED PAD, CONNECT TO PCB GROUND LAYER 06978-002 BCLK 6 PBDAT 7 PBLRC 8 RECDAT 9 RECLRC 10 MCLK/XTI XTO DGND DVDD CLKOUT Figure 6. Pin Configuration Table 9. Pin Function Descriptions Pin No.
PAGE 9
Data Sheet SSM2604 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –10 –20 –20 –30 –30 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 FREQUENCY (fS) 0 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.50 FREQUENCY (fS) Figure 7. ADC Digital Filter Frequency Response Figure 9. DAC Digital Filter Frequency Response 0.05 0.04 0.04 0.03 0.03 0.02 0.02 MAGNITUDE (dB) 0.05 0.01 0 −0.01 −0.02 −0.03 0.01 0 −0.01 −0.02 −0.03 −0.04 −0.
PAGE 10
SSM2604 Data Sheet DIGITAL DE-EMPHASIS 0 0.4 −1 0.3 −2 0.2 MAGNITUDE (dB) −4 −5 −6 −7 0 −0.1 −0.2 −8 −0.3 −9 0 4 8 12 16 FREQUENCY (kHz) −0.4 06978-007 −10 0.1 0 4 8 12 16 06978-010 MAGNITUDE (dB) −3 20 FREQUENCY (kHz) Figure 14. De-Emphasis Error, Audio Sampling Rate = 44.1 kHz Figure 11. De-Emphasis Frequency Response, Audio Sampling Rate = 32 kHz 0 0.4 −1 0.3 −2 −3 MAGNITUDE (dB) 0.1 0 −0.1 −0.2 −5 −6 −7 −0.
PAGE 11
Data Sheet SSM2604 THEORY OF OPERATION DIGITAL CORE Inside the SSM2604 digital core is a central clock source, called the master clock (MCLK), that produces a reference clock for all internal audio data processing and synchronization. When using an external clock source to drive the MCLK pin, great care should be taken to select a clock source with less than 50 ps of jitter. Without careful generation of the MCLK signal, the digital audio quality likely suffers.
PAGE 12
SSM2604 Data Sheet ANALOG INTERFACE BYPASS LINE INPUT Signal Chain The SSM2604 includes stereo single-ended line inputs to the on-board ADC. In addition, the line inputs can be routed and mixed directly to the output terminals via the BYPASS bit (Register R4, Bit D3). The SSM2604 also includes line outputs from the on-board DAC.
PAGE 13
Data Sheet SSM2604 SSM2604 to support the common universal serial bus (USB) clock rate of 12 MHz, or to support 24 MHz if the CLKDIV2 control register bit is activated. The user must set the appropriate sampling rate in the SR control bits (Register R8, Bit D2 to Bit D5). See Table 25 and Table 26 for guidelines. audio frame clock signal that separates left- and right-channel data on the PBDAT lines. The BCLK signal acts as the digital audio clock.
PAGE 14
SSM2604 Data Sheet 1/fS LEFT CHANNEL RIGHT CHANNEL RECLRC/ PBLRC BCLK X 1 2 3 4 N X X 1 2 N 3 X 06978-015 RECDAT/ PBDAT X = DON’T CARE. Figure 21. I2S Audio Input Mode 1/fS LEFT CHANNEL RIGHT CHANNEL RECLRC/ PBLRC BCLK 1 2 3 N 1 2 N 3 X X X 06978-016 RECDAT/ PBDAT X = DON’T CARE. Figure 22.
PAGE 15
Data Sheet SSM2604 SOFTWARE CONTROL INTERFACE CONTROL REGISTER SEQUENCING The software control interface provides access to the userselectable control registers and can operate with a 2-wire (I2C®) interface. 1. Enable all of the necessary power management bits of Register R6 with the exception of the out bit (Bit D4). The out bit should be set to 1 until the final step of the control register sequence. 2.
PAGE 16
SSM2604 Data Sheet TYPICAL APPLICATION CIRCUITS AVDD VMID AGND DVDD DGND SSM2604 PWROFF REF BYPASS ADC DAC ADC RLINEIN DAC ROUT DAC LOUT DIGITAL PROCESSOR ADC LLINEIN LINE BYPASS CLKOUT OSC MCLK/XTI CLK GEN XTO DIGITAL AUDIO INTERFACE CLKOUT CONTROL INTERFACE PBDAT RECDAT BCLK PBLRC RECLRC SDIN 06978-020 OSC SCLK Figure 26. Power Management Functional Location Diagram (Control Register R6, Bit D0 to Bit D7) +3.3V_VA L1 47uH,15mA C2 0.1uF 13 10M NC C13 1uF 17 C7 16 R3 5.
PAGE 17
Data Sheet SSM2604 REGISTER MAP Table 10. Register Map Reg.
PAGE 18
SSM2604 Data Sheet REGISTER MAP DETAILS LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00 Table 11. Left-Channel ADC Input Volume Register Bit Map D8 LRINBOTH D7 LINMUTE D6 0 D5 D4 D3 D2 LINVOL [5:0] D1 D0 Table 12.
PAGE 19
Data Sheet SSM2604 RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01 Table 13. Right-Channel ADC Input Volume Register Bit Map D8 RLINBOTH D7 RINMUTE D6 0 D5 D4 D3 D2 RINVOL [5:0] D1 D0 Table 14.
PAGE 20
SSM2604 Data Sheet ANALOG AUDIO PATH, ADDRESS 0x04 Table 15. Analog Audio Path Register Bit Map D8 0 D7 0 D6 0 D5 0 D4 DACSEL D3 BYPASS D2 0 D1 0 D0 0 Table 16. Descriptions of Analog Audio Path Register Bits Bit Name DACSEL Description DAC select. Allow DAC output to be mixed at device output terminal. Bypass select. Allow line input signal to be mixed at device output terminal. BYPASS Settings 0 = do not select DAC (default) 0 = bypass disable DIGITAL AUDIO PATH, ADDRESS 0x05 Table 17.
PAGE 21
Data Sheet SSM2604 POWER MANAGEMENT, ADDRESS 0x06 Table 19. Power Management Register Bit Map D8 0 D7 PWROFF D6 CLKOUT D5 OSC D4 1 D3 DAC D2 ADC D1 1 D0 LINEIN Table 20.
PAGE 22
SSM2604 Data Sheet DIGITAL AUDIO I/F, ADDRESS 0x07 Table 22. Digital Audio I/F Register Bit Map D8 0 D7 BCLKINV D6 MS D5 LRSWAP D4 LRP D3 D2 WL [1:0] D1 D0 FORMAT [1:0] Table 23.
PAGE 23
Data Sheet SSM2604 Table 26. Sampling Rate Lookup Table, USB Disabled (Normal Mode) MCLK (CLKDIV2 = 0) 12.288 MHz MCLK (CLKDIV2 = 1) 24.576 MHz 11.2896 MHz 22.5792 MHz 18.432 MHz 36.864 MHz 16.9344 MHz 33.8688 MHz 1 ADC Sampling Rate (RECLRC) 8 kHz (MCLK/1536) 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 8.0182 kHz (MCLK/1408) 11.025 kHz (MCLK/1024) 22.05 kHz (MCLK/512) 44.
PAGE 24
SSM2604 Data Sheet Table 27. Sampling Rate Lookup Table, USB Enabled (USB Mode) MCLK (CLKDIV2 = 0) 12.000 MHz 1 MCLK (CLKDIV2 = 1) 24.000 MHz ADC Sampling Rate (RECLRC) 8 kHz (MCLK/1500) 8 kHz (MCLK/1500) 8.0214 kHz (MCLK/1496) 8.0214 kHz (MCLK/1496) 11.0259 kHz (MCLK/1088) 12 kHz (MCLK/1000) 16 kHz (MCLK/750) 22.0588 kHz (MCLK/544) 24 kHz (MCLK/500) 32 kHz (MCLK/375) 44.118 kHz (MCLK/272) 44.118 kHz (MCLK/272) 48 kHz (MCLK/250) 48 kHz (MCLK/250) 88.
PAGE 25
Data Sheet SSM2604 ACTIVE, ADDRESS 0x09 Table 28. Active Register Bit Map D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 ACTIVE Table 29. Descriptions of Active Register Bit Bit Name ACTIVE Description Digital core activation control Settings 0 = disable digital core (default) 1 = activate digital core SOFTWARE RESET, ADDRESS 0x0F Table 30. Software Reset Register Bit Map D8 D7 D6 D5 D4 RESET [8:0] D3 D2 D1 D0 Table 31.
PAGE 26
SSM2604 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 0.60 MAX 16 PIN 1 INDICATOR 20 15 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD 5 11 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 6 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 27
Data Sheet SSM2604 NOTES Rev.