Datasheet

Data Sheet SSM2604
Rev. A | Page 21 of 28
POWER MANAGEMENT, ADDRESS 0x06
Table 19. Power Management Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
0
PWROFF
CLKOUT
OSC
1
DAC
ADC
1
LINEIN
Table 20. Description of Power Management Register Bits
Bit Name Description Settings
PWROFF Whole chip power-down control 0 = power up
1 = power down (default)
CLKOUT Clock output power-down control 0 = power up (default)
1 = power down
OSC
Crystal power-down control
0 = power up (default)
1 = power down
DAC DAC power-down control 0 = power up
1 = power down (default)
ADC ADC power-down control 0 = power up
1 = power down (default)
LINEIN Line input power-down control 0 = power up
1 = power down (default)
Power Consumption
Table 21.
Mode PWROFF CLKOUT OSC DAC ADC LINEIN
AVDD
(3.3 V)
DVDD
(3.3 V)
Unit
Record and Playback 0 0 0 0 0 0 9.41 3.7 mA
Playback Only
Oscillator Enabled
0
0
0
0
1
1
4.45
1.9
mA
External Clock 0 1 1 0 1 1 4.56 1.9 mA
Record Only
Line Clock 0 0 0 1 0 0 4.31 2.0 mA
Line Oscillator 0 0 1 1 0 0 4.33 2.0 mA
Analog Bypass
(Line Input or Line Output)
External Line 0 0 1 1 1 0 1.88 0.21 mA
Internally Generated Line 0 0 1 1 1 0 1.88 0.25 mA
Power-Down
External Clock 1 1 1 1 1 1 0.002 0.015 mA
Oscillator 1 1 1 1 1 1 0.002 0.015 mA