Datasheet

SSM2604 Data Sheet
Rev. A | Page 22 of 28
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 22. Digital Audio I/F Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
0
BCLKINV
MS
LRSWAP
LRP
WL [1:0]
FORMAT [1:0]
Table 23. Descriptions of Digital Audio I/F Register Bits
Bit Name Description Settings
BCLKINV BCLK inversion control 0 = BCLK not inverted (default)
1 = BCLK inverted
MS Master mode enable 0 = enable slave mode (default)
1 = enable master mode
LRSWAP
Swap DAC data control
0 = output left- and right-channel data as normal (default)
1 = swap left- and right-channel DAC data in audio interface
LRP Polarity control for clocks in right-justified,
left-justified, and I
2
S modes
0 = normal PBLRC and RECLRC (default), or DSP Submode 1
1 = invert PBLRC and RECLRC polarity, or DSP Submode 2
WL [1:0] Data-word length control 00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
FORMAT [1:0] Digital audio input format control 00 = right justified
01 = left justified
10 = I
2
S mode (default)
11 = DSP mode
SAMPLING RATE, ADDRESS 0x08
Table 24. Sampling Rate Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
0 CLKODIV2 CLKDIV2 SR [3:0] BOSR USB
Table 25. Descriptions of Sampling Rate Register Bits
Bit Name Description Settings
CLKODIV2 CLKOUT divider select 0 = CLKOUT is core clock (default)
1 = CLKOUT is core clock divided by 2
CLKDIV2 Core clock divide select 0 = core clock is MCLK (default)
1= core clock is MCLK divided by 2
SR [3:0] Clock setting condition See Table 26 and Table 27
BOSR
Base oversampling rate
USB mode:
0 = support for 250 f
S
based clock (default)
1 = support for 272 f
S
based clock
Normal mode:
0 = support for 256 f
S
based clock (default)
1 = support for 384 f
S
based clock
USB USB mode select 0 = normal mode enable (default)
1 = USB mode enable