User's Manual

ManualsBrandsAOC ManualsTVs & monitors41A50-144

SERVICE MANUAL

SPECTRUM Series

LCD Monitor

LM-700/LM-700A

P/N : 41A50-144

Summary of content (82 pages)

PAGE 1
SERVICE MANUAL SPECTRUM Series LCD Monitor LM-700/LM-700A P/N : 41A50-144
PAGE 2
THESE DOCUMENTS ARE FOR REPAIR SERVICE INFORMATION ONLY. EVERY REASONABLE EFFORT HAS BEEN MADE TO ENSURE THE ACCURACY OF THIS MANUAL; WE CANNOT GUARANTEE THE ACCURACY OF THIS INFORMATION AFTER THE DATE OF PUBLICATION AND DISCLAIMS RE LIABILITY FOR CHANGES, ERRORS OR OMISSIONS, MANUFACTURE DATA : JULY.
PAGE 3
TABLE OF CONTENTS PAGE 1. SPECIFICATIONS .................................................................................................... 1-1 GENERAL SPECIFICATIONS ...................................................….............. 1-2 LCD MONITOR DESCRIPTION .................................................................. 1-3 INTERFACE CONNECTOR .................................................................……. 3 3 4 4 2. PRECAUTION AND NOTICES ...................................................
PAGE 4
1. SPECIFICATIONS FOR LCD MONITOR 1-1 1. General specifications LCD-PANEL : Active display area Pixel pitch Pixel format 17 inches diagonal 0.264 mm x 0.264 mm 1280 x 1024 RGB vertical stripe arrangement 2. Display Color : 8-bit, 16.7 million colors 3.
PAGE 5
1-2 LCD MONITOR DESCRIPTION The LCD MONITOR will contain an main board, an Inverter module, keyboard and External Adapter which house the flat panel control logic, brightness control logic, DDC and DC-DC conversion The Inverter module will drive the backlight of panel . The Adapter will provides the 12V DC-power 5 Amp to Main-board and Inverter module . Monitor Block Diagram Flat Panel and CCFL backlight CCFT Drive.
PAGE 6
2. PRECAUTIONS AND NOTICES 2-1 ASSEMBLY PRECAUTION (1) Please do not press or scratch LCD panel surface with anything hard. And do not soil LCD panel surface by touching with bare hands (Polarizer film, surface of LCD panel is easy to be flawed) In the LCD panel, the gap between two glass plates is kept perfectly even to maintain display characteristic and reliability.
PAGE 7
3. OPERATING INSTRUCTIONS This procedure gives you instructions for installing and using the LM700 LCD monitor display. 1. Position the display on the desired operation and plug–in the power cord into External Adapter AC outlet. Three-wire power cord must be shielded and is provided as a safety precaution as it connects the chassis and cabinet to the electrical conduct ground.
PAGE 8
4. ADJUSTMENT 4-1 ADJUSTMENT CONDITIONS AND PRECAUTIONS Adjustments should be undertaken only on following function : contrast, brightness focus, clock, h-position, v-position, red, green, blue since 6500 color & 7800 color. 4-2 ADJUSTMENT METHOD Press MENU button to activate OSD Menu or make a confirmation on desired function, Press Left/Right button to select the function or done the adjustment. 1.
PAGE 9
. 10. 11. 12. 13. 14. adjust the GREEN on OSD, until chroma 7120 indicator reached G=100 adjust the BLUE on OSD, until chroma 7120 indicator reached B=100 repeat above procedure ( item 8,9,10) until chroma 7120 RGB value meet the tolence =100±2 switch the chroma-7120 to xyY mode With press “MODE” button Adjust the Contrast on OSD window until the Y measurement on chroma 7120 reached the value Y= 180 cd/m2 Press 78 on OSD window to save the adjustment result b.
PAGE 10
4-3 2. Clock adjustment Set the Chroma at pattern 63 (cross-talk pattern) or WIN98/95 shut-down mode (dot-pattern). Adjust until the vertical-Stripe-shadow as wide as possible or no visible. This function is adjust the PLL divider of ADC to generate an accurate pixel clock Example : Hsyn = 31.5KHz Pixel freq. = 25.175MHz (from VESA spec) The Divider number is (N) = (Pixel freq.
PAGE 11
5. 5-1 CIRCUIT-DESCRIPTION SPECIAL FUNCTION with PRESS-KEY A). press Menu button during 2 seconds along with plug-in the DC Power cord: That operation will set the monitor into “Factory- mode”, in Factory mode we can do the White balance adjustment with RS232 , and view the Backlight counter (this counter is use to record the panel activate hours ,for convenient the maintainer to check the panel backlight life time) In Factory mode, OSD-screen will locate in left top of screen.
PAGE 12
5-3 SIMPLE-INTRODUCTION about LM700 chipset 1. GMZAN1 ( all-in-one chip solution for ADC, OSD, scalar and interpolation) : USE for computer graphics images to convert analog RGB data to digital data with interpolation process, zooming, generated the OSD font , perform overlay function and generate drive-timing for LCD-PANEL. 2.
PAGE 13
Main-board Block diagram Input analog RGB & H,V,& ddc signal & Rs232 communication GMZAN1 (U200) Data Digital RGB DDC-chip LVDS chip (U601, U602) PANEL Panel Control Signal: Dhs, Dvs, Dclk Oscillator 50 mhz Panel Power 5V Communication signal: Hclk,Hfs,Hdata0 Panel-Power Control (U202) MCU ( U302 ) Crystal 20 mhz DC 12V 5Amp Keyboard module INVERTER module EXTERNALADAPTER 12
PAGE 14
5-4 SOFTWARE FLOW CHART I. Power-On Subrotine CHART POWER-ON START Initial MCU I/O, Interrupt vector & Ram Yes Initial 1.POC (backlight counter) 2. Clr all mode value Check Eeprom is empty ? No Check White-balance data(6500 & 7800) same with the OK backup data ? Check POC( backlight counter) data same with the backup data ? IF not same, overwrite the data with backup value.
PAGE 15
II. MAIN SUBROTINE LOOP Main loop start Process Power-saving status ( according to below flow-chart result) ) Check GMZAN IFM status .is change or not.
PAGE 16
6. A). Interface-Board Trouble-Shooting chart *Use the PC Win 98 white pattern, with some icon on it, and Change the Resolution to 640x480 60 Hz / 31 KHz **NOTICE : The free-running freq. of our system is 48 KHz / 60 Hz, so we recommend to use another resolution to do trouble shooting, this trouble shooting is proceed with 640x480 @60Hz 31Khz I. NO SCREEN APPEAR DC-Power Part Measured Input DC-voltage ( J1)= 12 V? Measured U305 AIC 1084 pin 2 = 3.3V? Measured U904 LT1117 pin 2= 3.
PAGE 17
PANEL-POWER CIRCUIT Check the PPWR panel power relative circuit, R223, Q200,U202(pin 5,6,7,8) In normal operation, when LED =green, R223 should =0 v, If PPWR no-response when the power switch Turn on and turn off, replace the U200-GMZAN1 NG check R225 should have response from 12V to 0V When we switch the power switch from on to off OK,R225 have response Yes NG, no Voltage Check U202 pin 1,2,3,4= 5V Measured the U202 pin 5,6,7,8= 5 V? Replace U202 ( Nmos, SI9933) OK NG OK Check U304 relative circ
PAGE 18
II (a) THE SCREEN is Abnormal , stuck at white screen, OSD window can’t appear, but keyboard & LED was normal operation. At general, this symtom is cause by missing panel data or panel power, so we must check our wire-harness which connected to panel or the panel power controller (U202) NG Check if the Wire harness from CN601 & CN602 loose? Check the wire on both Panel-side and Mainboard side. Tighten it.
PAGE 19
KEYBOARD BLOCK check Check U302 MCU pin 43,42,41,40,39 at High state(5V)? without press any key NG Mechanical was stuck, Check ! OK NG Press power key and check U302 pin 43 = low (0V) ? Replace Tact-switch SW105 at keyboard if still no work replace U302 MCU at main-board and check MCU relative reset circuit, and crystal OK Check U302 pin 38 (LED green) will have transition from hi to low or low to hi when we press the power key?? OK If still no Led green indicator, check Q102, R106 & LED at keyboard
PAGE 20
POWER-BLOCK check **Note : the Waveform of U304 pin 2 can determined the power situation 1. 2. 3. stable rectangle waveform with equal duty, freq around 150K-158KHz that means all power of this interface board is in normal operation ,and all status of 5V & 3.3V is working well unstable or uneven rectangle waveform without same duty, that means ABNORMAL operation was happened, check 3.
PAGE 21
III.ALL SCREEN HAS INTERFERENCES OR NOISE, CAN’T BE FIXED BY AUTO KEY ** NOTE: There is so many kind of interferences, 1). One is cause by some VGA-CARD that not meet VESA spec or power grounding too bad that influence our circuit 2).other is cause by external interferences, move the monitor far from electronic equipment.
PAGE 22
There is an interferences in DOS MODE NOTE :the criteria of doing AUTO-CONFIGURATION : must be a full-size screen, if the screen not full , the autoconfiguration will fail. So in dos mode ,just set your “CLOCK” in OSD-MENU to zero or use some EDITOR software which can full fill the whole screen (ex: PE2, HE) and then press “AUTO” Or you can use “DOS1.EXE” which attached in your Driver disk to optimize DOS mode performance V.
PAGE 23
6 B). Inverter –MODULE Spec &Trouble Shooting Chart In LM700 model , we use CHI-MEI panel, and the INVERTER PROVIDER is SAMPOCORPORATION I.) TROUBLE SHOOTING OF CHI-MEI INVERTER (part no : 79AL17-1-S) TYPE: L0037 FOR CHI-MEI 17”PANEL SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 1.SAMPO PART NO .: L0037 ,AOC PART NO.: 79AL17-1-S 2.SCOPE : this is to specify the requirements of the subject parts used in CHI-MEI (M170E1) 17 inch (4 C.C.F.L.) LCD monitor. 3.
PAGE 24
SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 5.FUNCTION SPECIFICATIONS: The data test with the set of SAMPO, and the test circuit is as below. SYMBOL MIN. TYP. MAX. UNIT Input voltage Vin 10.8 12 13.2 V Input current Iin -- 2200 2500 mA output current Iout ITEM adj:0v( min.) REMARK FOR 1 CCFL (min) 2.1 2.6 3.1 mA LOAD:120KΩ FOR 1 CCFL Output current Iout adj.:5 v(max.) (max) 5.5 6.0 6.5 mA Frequency F 40 50 60 KHZ H.
PAGE 25
SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) D D S S D D G D S S D G D D S S 7.
PAGE 26
SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 8.PART LIST 8-1 COMPONENTS LIST: NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK 1. CON1 CONNECTOR VCNCP0015-EJSTA 1 S5B-PH-SM3-TB JST 2. CON2,3 〃 VCNCP0014-PJSTA 2 SM04(4.0)B.BHS-1-TB JST GL SM02(4.0)-WH2 GEAN-LEA VCNCP0014-ZGLEA 3. R1,2 RESISTOR VRMHNVA--103J-A 2 SMD 0603 10KΩ 5% YAGEO 4. R3,4 〃 VRMHNVA--683J-A 2 SMD 0603 68KΩ 5% YAGEO 5. R5,6 〃 VRMHNVA--912J-A 2 SMD 0603 9.
PAGE 27
SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 8-2 COMPONENTS LIST: NO. REF. PART NAME PART NUMBER QTY DESCRIPTION 26. C6 〃 VCLRCN1HB102K-A 1 SMD 0805 1000PF/50V TDK 27. C10,11 〃 VCLRCN1EB333K-A 2 SMD 0805 0.033 µF/25V TDK 28. C12,13 〃 VCMEBF2AB184J-P 2 DIP 0.18µF/100V ARCO DIP 0.18µF/100V THOMSON 4 DIP 22PF/3KV 10% TDK VCMECF2AC184J-P 29 C14,15,19, CAPACITOR VCDSEU3SL220K-20 SUPPLIER REMARK 30.
PAGE 28
SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 9. TROUBLE SHOOTING 9-1 NO POWER: . CHECK ON FUSE F1 Vin=12 PASS PASS TO CHANGE F1= 4.
PAGE 29
SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 9-2 HIGHT VOLTAGE PROTECTION: 1. SHORT R30 OPEN LOAD 2.
PAGE 30
SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 9-4. ENBALE ABNORMALITY: IF ENBALE ABNORMALITY 1.
PAGE 31
-9- SAMPO CORPORATION TROUBLE SHOOTING OF CHI-MEI INVERTER ( DIVTL0037-D42- -) 9-6 TRANSFORMER ABNORMALITY: IF TRANSFORMER ABNORMALITY TO CHECK C3&C4 CHIP OUTLINE OR TRANSFORMER PASS FAIL TO CHANGE ON C3&C4 OR TRANSFORMER FUNCTION TEST OK! 10. INSTRUMENTS FOR TEST: 1. DC POWER SUPPLY GPS-3030D 2. AC VTVM VT:-181E 3. DIGITAL MULTIMERTER MODEL-34401 4. HIGHTVOLT PROB MODEL-1137A 5.SCOPE MODEL-V-6545 6.
PAGE 32
6 C). ADAPTER-MODULE Trouble shooting chart The following spec & block-diagram is offer by CHI-SAM –COMPANY, for External Adapter part number : 80AL17-1-CH ( Black), 80AL17-2-CH ( White) AC ADAPTER CH-1205 TROUBLE SHOOTING NO VOLTAGE O/P CHECK BD101 AC VOLT. I/P OK ? NO REPLACE F101 NO REPLACE BD101 YES CHECK BD101 DC VOLT. O/P OK ? YES CHECK U101 PIN7 12~15Vdc OK ? NO CHECK R115,D103,U101 NG ? NO CHECK C110,U101 NG ? NO CHECK Q101 NG YES CHECK U101 PIN4 FREQ.
PAGE 33
I.
PAGE 34
IV. ADAPTER BOM LIST ( PART no. 80AL15-2-LI) Item Reference Part Quantity Cat.NO. 1 BD101 DIODE BRIDGE KBL405G 600V/4A 1 PCS 15D7L405G6 2 CN101 AC POWER SOCKET 1 PCS 64P21-0001 3 BEAD1,BEAD2,BEAD3,BEAD4 BEAD 3.5*3.2*1.
PAGE 35
41 PCB PCB FOR CH-1205 REV:D 1 PCS 11S43-0030 42 R117 RES 100 1/8W +-5% SMD(0805) 1 PCS 2242510000 43 J109,J110 RES 0 OHM 1/4W +-5% SMD(1206) 2 PCS 2243500000 44 R143 RES 1.
PAGE 36
86 FOR FRONT HEATSINK 導熱墊片 TCR- 05 15*25-ASAHI 1 PCS 85011-0001 87 FOR FRONT HEATSINK 導熱墊片 TCR- 10 1 PCS 85100-0001 88 3M擋牆膠帶#44 1L 35*40mm 1 PCS 80400-0001 89 FRONT COVER 129.3*63.8*19.34mm 1 PCS 0810400020 90 BASE COVER 129.3*63.8*18.7mm 1 PCS 0820400020 91 DC OUTPUT POWER CABLE UL1185#18AWG ψ5.5*ψ2.5 *20.
PAGE 37
6 D). AUDIO-MODULE Trouble shooting chart I.) NO VOICE OUTPUT Plug-out the DC power , make sure the monitor is in OFF status . NG Check J1,J2 is well connected? Measured J2 pin 4,5 & 2,3 is well connected ? Use OHM-METER measure U1 pin 2, 4 (channel-A ) is speaker well connected? Measure U1 pin 10,12 ( channel B) is speaker well connected ? YES YES ] Check is speaker open circuit ? Plug-in the DC power, set the monitor ON status .
PAGE 38
II.) SOUND DISTORTION NG Check U1 pin 2, 4 10, 12 is the voltage output = VCC / 2 . ? Check U1 YES CHECK SPEAKER AUDIO BOM Bill Of Materials September 7,2001 18:09:14 Page1 Item Quantity Reference Part ______________________________________________ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 3 1 1 2 1 1 1 2 1 1 1 3 1 1 2 1 2 2 1 1 1 C1,C2,C4 C3 C5 C6,C7 C8 C9 D1 J1,J3 J2 J4 J5 VR1,R1,R2 R3 R4 R5,R6 R7 R9,R8 R11,R10 R12 S1 U1 1uF 2200uF/25V 10uF/50V 0.
PAGE 39
GMZAN1 The gmZAN1device utilizes Genesis’ patented third-generation Advanced Image Magnification technology as well as a proven integrated ADC/PLL to provide excellent image quality within a cost effective SVGA/XGA LCD monitor solution. As a pin-compatible replacement for the gmB120, the gmZAN1 incorporates all of the gmB120 features plus many enhanced features; including 10-bit gamma correction, Adaptive Contrast Enhancement (ACE) filtering, Sync On Green (SOG), and an enhanced OSD. 1.
PAGE 40
1.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 1 : Analog-to-Digital Converter PIN # Name I/O Description 77 ADC_VDD2 78 ADC_GND2 79 ADC_VDD1 80 ADC_GND1 81 SUB_GNDA 82 ADC_GNDA 84 ADC_VDDA 83 Reserved 85 ADC_BGNDA 88 ADC_BVDDA 86 BLUE- I Analog ground for the blue channel. Must be directly connected to the analog system ground plane. Analog power for the blue channel. Must be bypassed with 0.
PAGE 41
Table 2 : Host Interface (HIF) / External On-Screen Display PIN # Name I/O Description 98 HFS I Host Frame Sync. Frames the packet on the serial channel. 103 HCLK I Clock signal input for the 3-wire serial communication. 99 HDATA I/O 100 RESETn I Resets the gmZAN1 chip to a known state when low. 101 IRQ O Interrupt request output. 115 OSD-HREF O HSYNC output for an external OSD controller chip. 116 OSD-VREF O VSYNC output for an external OSD controller chip.
PAGE 42
Table 3 : Clock Recovery / Time Base Conversion PIN # Name 125 DVDD 127 DAC_DGNDA 128 DAC_DVDDA 129 PLL_DVDDA 130 Reserved 131 PLL_DGNDA 132 SUB_DGNDA 133 SUB_SGNDA 134 PLL_SGNDA 135 Reserved 136 PLL_SVDDA 137 DAC_SVDDA 138 DAC_SGNDA 139 SVDD 141 142 TCLK XTAL 143 PLL_RVDDA I/O Description I O Digital power for Destination DDS (direct digital synthesizer). Must be bypassed with a 0.1uF capacitor to digital ground plane. Analog ground for Destination DDS DAC.
PAGE 43
Table 4.
PAGE 44
PIN # Name I/O 2pxl/clk 8bit 2pxl/clk 6-bit Description 1pxl/clk 1pxl/clk 8-bit 6-bit 63 PD7 O EG3 EG1 G3 G1 64 PD6 O EG2 EG0 G2 G0 66 PD5 O ER7 EG5 R7 R5 67 PD4 O ER6 ER4 R6 R4 68 PD3 O ER5 ER3 R5 R3 69 PD2 O ER4 ER2 R4 R2 70 PD1 O ER3 ER1 R3 R1 71 PD0 O EG2 ER0 R2 R0 43 PdispE O TFT This output provides a panel display enable signal that is active when flat panel data is valid. 74 PHS O This output provides the panel line clock signal.
PAGE 45
1.
PAGE 46
1.5 Operating Modes The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows: z The Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by SCLK DDS (direct digital synthesis) and the PLL. z The Panel Clock is the timing clock for panel data at the single pixel per clock rate. The actual PCLK to the panel may be one-half of this frequency for double-pixel panel data format.
PAGE 47
1.5.4 Downscaling Panel Clock frequency < Source Clock frequency Panel Hsync frequency < Input Hsync frequency Panel Vsync frequency = Input Vsync frequency This mode is used when the input resolution is greater than the panel resolution, to provide enough of a display to enable the user to recover to a supported resolution. The input clock is operated at a frequency less than that of the input pixel rate(under-sampled horizontally) and the scaling filter is used to drop input lines.
PAGE 48
2. FUNCTIONAL DESCRIPTION Figure 3 below shows the main functional blocks inside the gmZAN1 2.1 Overall Architecture Figure 3. Block Diagram for gmZAN1 On-Screen Display Control Analog RGB MCU Triple ADC Source Timing Measurement / Generation Scaling Engine Host Interface Gamma Control (CLUT) + Dither Clock Recovery Panel Timing Control Panel Pixel Clock Generator Clock Reference 2.2 Clock Recovery Circuit The gmZAN1 has a built-in clock recovery circuit.
PAGE 49
The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS (direct digital synthesis) technology the clock recovery circuit can generate any SCLK clock frequency within this range. The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2). It is generated by a circuit virtually identical to the clock recovery circuit. The difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input.
PAGE 50
The table below summarizes the characteristics of the clock recovery circuit. Table 7. Clock Recovery Characteristics Minimum 10MHz SCLK Frequency Sampling Phase Adjustment Typical Maximum 135 MHz 0.5 ns/step, 64 steps Patented digital clock synthesis technology makes the gmZAN1 clock circuits very immune to temperature/voltage drift. 2.2.1 Sampling Phase Adjustment The ADC sampling phase is adjusted by delaying the Hsync input at the programmable delay cell inside the gmZAN1.
PAGE 51
2.3 Analog-to-Digital Converter 2.3.1 Pin Connection The RGB signals are to be connected to the gmZAN1 chip as described in Table 8 and Table 9. Table 8.
PAGE 52
2.3.2 Sync. Signal Support The gmZAN1 chip supports digital separate sync (Hsync/Vsync), digital composite sync, and analog composite sync (also known as sync-on-green). All sync types are supported without external sync separation / extraction circuits.
PAGE 53
The display start/end registers store the first and the last pixels/lines of the last frame that have RGB data above a programmed threshold. The reference point of the STM block is the same as that of the source timing generator (STG) block: z The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high. z The first line: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high.
PAGE 54
2.5.1 Scaling Filter The gmZAN1 scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip Inc. and provides high quality scaling of real time video and graphics images. This is Genesis’ third generation scaling technology that benefits from the expertise and feedback gained by supporting a wide range of solutions and applications. 2.5.2 Gamma Table The gamma table is used to adjust the RGB data for the individual display characteristics of the TFT panel.
PAGE 55
Table 13. gmZAN1 TFT Panel Interface Timing Signal Name PVS Period PHS PCLKA, PCLKB*4 Data Frequency Front porch Back porch Pulse width PdispE Disp. Start from VS PVS set up tp PHS PVS hold from PHS Period Front porch Back porch Pulse width PdispE Disp. Start fom HS Frequency Clock (H) *2 Clock (L) *2 Type Set up *3 Hold *3 width t1 Min 0 Typical 16.
PAGE 56
Figure 7.
PAGE 57
Figure 8. Data latch timing of the TFT Panel Interface (a) Two pixel per clock mode in TFT PDE t16 t13 t15 PCLK t14 t16 ER R0,(N:0) R2,(N:0) EG G0,(N:0) G2,(N:0) EB B0,(N:0) B2,(N:0) OR R1,(N:0) R3,(N:0) OG G1,(N:0) G3,(N:0) OB B1,(N:0) B3,(N:0) t17 R4,(N:0) (b) One pixel per clock mode in TFT PDE t16 t13 PCLK t15 t14 R(n:0) R0 G(n:0) G0 B(n:0) B0 t17 t16 R1 2.6.
PAGE 58
2.6.2.1 State 0 (Power Off) The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled. 2.6.2.2 State 1 (Power On) Intermediate step 1. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is forced low (inactive). 2.6.2.3 State 2 (Panel Drive Enabled) Intermediate step 2.
PAGE 59
2.6.3 Panel Interface Drive Strength As mentioned previously, the gmZAN1 has programmable output pads for the TFT panel interface. Three groups of panel interface pads (panel clock, data, and control) are independently controllable and are programmed using API calls. See the API reference manual for details. Table 14.
PAGE 60
2.7.1 Serial Communication Protocol In the serial communication between the microcontroller and the gmZAN1, the microcontroller always acts as an initiator while the gmZAN1 is always the target. The following timing diagram describes the protocol of the serial channel of the gmZAN1 chip. Figure 10.
PAGE 61
Table 15 summarizes the serial channel specification of the gmZAN1. Refer to Figure 10 for the timing parameter definition. Table 15. gmZAN1 Serial Channel Specification Parameter Word Size (Instruction and Data) HCLK low to HFS high (t1) HFS low to HCLK inactive (t2) HDATA Write to Read Turnaround Time (t3) HCLK cycle (t4) Data in setup time (t5) Data in hold time (t6) Data out valid (t7) Min. --100 ns 100 ns 1 HCLK cycle 100 ns 25 ns 25 ns 5 ns Typ. 12 bits Max.
PAGE 62
2.8.1 OSD Color Map Both the internal and external OSD display use a 16 location SRAM block for the color programming.
PAGE 63
To improve the appearance and make it easy to find the OSD window on the screen, the user may select optional shadowing (3D effect). The “Shadow” feature operates in the same manner as in the B120; that is, it produces a region of half intensity (scaler data) pixels of the same width and height as the OSD window, but offset to the right and down by 8 pixels/lines (the border width setting has no effect).
PAGE 64
3. ELECTRICAL CHARACTERISTICS Table 20. Absolute Ratings Parameter PVDD CVDD Vin Operating temperature Storage temperature Maximum power consumption Min. Typ. Vss-0.5 volt 0 degree C -65 degree C Max. 5.6 volts 5.6 volts Vcc+0.5V 70 degree C 150 degree C ~2W Note Table 21. DC Electrical Characteristic Parameter Min. Typ. Max. Note PVDD 3.15 volts 3.3 volts 3.47 volts CVDD 3.15 volts 3.3 volts 3.47 volts Vil (COMS inputs) 0.3*CVDD Vil (TTL inputs) 0.8 volts Vih (COMS inputs) 0.7 * CVDD 1.
PAGE 65
7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY For temporary, this page still not available.
PAGE 66
PARTS LIST OF CABINET LOCATION T780KMGHBAA0A AUPC780A1 CBPC780GM DCPC780A3 KEPC780EK SPECIFICATION 17” LCD AUDIO BOARD 17” CONVERSION BOARD 17” DC POWER BOARD KEYBOARD 12A 381 1 15A 5684 1 15A 5689 1 15A 5689 2 26A 800 13 33A 3647 1 33A 4058 YL 33A 4060 YL 33A 4061 YL 33A 4062 YL 33A 4063 YL 34A 756 1Y L 34A 757 Y 1L 34A 758 YL 34A 759 Y 3L 34A 760 YL 34A 761 YL 37A 443 1 40A 155 237 41A 401 948 1A 44A 3147 1 44A 3148 1 44A 3234 1 44A 3234 2 44A 3234 5 44A 3253 1 45A 113 1 45A 114 1 45A 116 1 52A 1208 A
PAGE 67
PARTS LIST OF CABINET ( continue) LOCATION T780KMGHBAA0A Q1A Q1A Q1A 750A SPECIFICATION 1030 10128 1030 12128 1030 12128 LCD 170 3 SCREW SCREW 3X12mm SCREW 3X12mm LCD-PANEL M170E1-01 BY CHI-MEI 66
PAGE 68
PARTS LIST OF CONVERSION BOARD LOCATION CN303 CN302 CN602 CN601 R319 JP201 JP303 CN200 U302 C307 C309 C310 C312 C927 C928 C945 FB301 T300 T300 L905 VR501 X300 U201 CN301 CBPC780GM 33A 38025H 33A 38029H 33A 3802- 10H 33A 3802- 14H 33A 8009233A 80093 33A 80093 33A 88102 33A 801314 40A 15243 44A 32318 56A 112561 67A 305331 67A 305331 67A 305331 67A 305331 67A 305331 67A 305331 67A 309471 71A 5528 73A 253108 73A 253108 73A 2594 75A 335103 90A 3722 93A 2255 93A 2257 95A 90016A L H M 6 6 6 6 6 6 3T Y LI 67
PAGE 69
LOCATION U601 U602 U200 U304 U305 U202 U904 U904 U401 U401 U203 U300 U300 Q200 Q304 D303 D303 RP300 L207 R200 R201 R202 R203 R207 R208 R229 R317 R340 R603 R905 R218 R219 R220 R227 R213 R214 R216 R217 R223 R224 R225 R300 R301 R311 R313 R315 R326 R327 R328 R329 R209 R210 R204 R205 R206 C229 C230 C231 C232 C233 C234 C251 C606 C608 C614 AI780GM 56A 56156A 56156A 56256A 56356A 56356A 56656A 58556A 58556A 74F56A 74F56A 113356A 113356A 113357A 41757A 41757A 75457A 75461A 12561A 060361A 060361A 060361A 060361A 060
PAGE 70
LOCATION C616 C201 C202 C204 C205 C207 C208 C209 C210 C211 C212 C213 C215 C217 C218 C219 C220 C221 C222 C223 C225 C226 C227 C228 C237 C244 C245 C246 C300 C304 C308 C311 C405 C601 C602 C604 C618 C619 C939 C940 C941 C942 C944 C250 C303 C306 CP301 CP302 C605 C607 C613 C615 C620 C200 C203 C206 C214 C216 C224 C305 C403 AI780GM 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A
PAGE 71
LOCATION C603 C943 C313 C314 L200 L201 L202 L203 L300 L900 L601 L602 L603 L604 R215 L601 L602 L603 L604 R215 MTG U3 D200 D201 D208 D209 D210 D200 D201 D208 D209 D210 D200 D201 D208 D209 D210 D300 D300 D300 D202 D203 D204 D205 D206 D207 D301 D302 D202 D203 D204 D205 D206 D207 D301 D302 D202 D203 D204 D205 D206 D207 D301 D302 AI780GM 67A 67A 67A 67A 71A 71A 71A 71A 71A 71A 71A 71A 71A 71A 71A 71A 71A 71A 71A 71A 87A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 93A 9
PAGE 72
PARTS LIST OF KEY PC BOARD LOCATION TP101 TP102 J7 Q101 Q102 R101 R102 R103 R104 R105 R106 R107 R108 C101 SW1 SW2 SW3 SW4 SW5 LED1 JP2 J101 Quantity KEPC780EK 9A 9A 33A 40A 57A 57A 61A 61A 61A 61A 61A 61A 61A 61A 65A 77A 77A 77A 77A 77A 81A 88A 95A 95A 715A 308 308 3252 152 419 419 6021 6021 6021 6021 6021 6021 6021 6022 450 600 600 600 600 600 13 304 90 8014 778 1 1 3 44 PP PP 0352 0352 0352 0352 0352 0352 0352 2152 104 1 1 1 1 1 1 1 23 9 1 H T T T T T T T T T T 7T G G G G G B S H 6 A 71 SPECIFIC
PAGE 73
PARTS LIST OF DC-POWER BOARD LOCATION P4 P3-1 C71 J2 J1 JP3 DCPC780A3 33A 33A 67A 88A 88A 89A 715A 3278 3278 305 302 304 171 851 Quantity 2 3 331 4 1 27 2 1 1 1 1 1 1 1 6 S S A SPECIFICATION 2P PLUG B2B-XHA/JST B2B-XHA/JS 3P PLUG B3B-XHA/JST B3B-XHA/JS 330uF+－ 20% 35V 3.
PAGE 74
9. POWER SYSTEM AND CONSUMPTION CURRENT ADAPTER MODULE Input AC 110V, 60Hz/240V, 50Hz Output DC 12V 5A INVERTER MODULE Input DC 12V Output AC 1500V/30K-80KHz Current 14mA Main board power system LM2596S-5, 12V to 5V (5A SPEC) 5V To CPU, Eeprom, 24c21, control-inverter-on.off 860mA when Cable not Connected 841mA when Normal operation To Chi-Mei Panel around 1250mA AIC1084, 5V to 3.3V (5A SPEC) LT1117 5V to 3.3V ( 800mAspec) 3.
PAGE 75
10. PCB LAYOUT LVDS power ( LT1117) DDC chip Input Connector LVDS Gmzan1 AIC1084 5V to 3.
PAGE 76
11. SCHEMATIC DIAGRAM I). TOP-LEVEL FLOW PAGE 4 +12V +3.3V +5V POWER MFB1 MFB2 +12V MFB1 MFB2 +3.3V Power block +5V PAGE 3 +5V PAGE 2 LVDS block PAGE 6 HDATA0 MFB2 MFB7 MFB8 MFB9 TCLK1 HDATA0 MFB2 MFB7 MFB8 MFB9 TCLK1 ERED ERED EGRN EGRN EBLU EBLU ORED ORED OGRN SCL SDA SCL SDA OGRN OBLU OBLU PCLK IRQ PCLK IRQ PHS HFS HCLK /VGA_CON RST RST1 MCU MICRO CONTROLLER RXD TXD HFS HCLK /VGA_CON PHS PVS PVS PDISPE PDISPE RST RST1 RXD TXD LVDS .
PAGE 77
+5V +3.3V II). GMZAN1 Block L200 DVDDA 8 7 6 5 +3.3V 3.3V 3.3V 600(1206) DVDDA VDDA SVDDA 103 101 98 HCLK IRQ HFS +5V 107 R327 R317 0 106 R316 NC 124 123 109 110 111 112 113 10 K R227 GND /VGA_CON VDDA 100 C251 D210 10nF 5.
PAGE 78
AVDD_3.3 C601 EVEN EGRN[0..7] EBLU[0..7] PD36 PD37 PD0 PD1 PD2 PD3 PD4 PD5 51 52 54 55 56 3 50 2 PD38 PD39 PD6 PD7 PD8 PD9 PD10 PD11 4 6 7 11 12 14 8 10 PD40 PD41 PD12 PD13 PD14 PD15 PD16 PD17 15 19 20 22 23 24 16 18 25 27 28 30 31 PCLKB 1 9 C602 + C603 0.1uF 100uF 26 V ERED[0..7] 0.
PAGE 79
+5V MCU Block R431 10 K(OP) (Panel-Select)* K/E Select 8XC51/PLCC U302 PSEN ALE/PROG RST R340 1 2 3 4 5 6 7 8 9 C306 C305 C304 100uF 0.1 uF 4 3 2 44 35 HEADER 9 CP301 CP302 1000 pF 1000 pF 5 22 33 pF CN302 KEY1(ORANGE?) KEY2(GREEN?) KEY3(AUTO) KEY4(ENTER) KEY5(RIGHT) KEY6(LEFT) KEY7(POWER) 6 XTAL1 GND 21 R329 10 K WP 36 37 38 39 40 41 42 43 1 VCC EA/VP 20MHz R328 10 K GND +A5V XTAL2 R341 0 TEST(OP) C303 32 33 7 20 X300 KEY +5V 8 RST1 /VGA_CON GND P0.7/AD7 P0.
PAGE 80
+5V +12V R905 0 U304 LM2596S-5.0 CN301 +12V POWER R904 TO263 FB301 VIN /ON GND 1 C307 C308 330 uF/35V 0.1 uF Vout 4 0(OP) 2 T300 5 3 INDUCTOR FBK R902 3K(OP) 33 uH C309 D300 C941 0.1 uF 330 uF/35V B320 R903 1K(OP) GND GND POWER Block GND +5V +A5V L905 C945 CHOKE 470uF/16V GND +3.3V +5V U305 AIC 1084 L300 Vout C311 0.
PAGE 81
12.) ADAPTER SCHEMATIC CH-1205 CN101 AC SOCKET C116 1000P/500V R101 NTCR 3/5A F101 2A/250V L101 2mH R102 470K 1/4W L102 18mH BD101 KBL405G C104 120U/400V C105 103P/500V C101 CY 2200P/250V + R132 24 1/4W R131 24 1/4W R133 24 1/4W 4 R111 43K/3W(MOF) - T101 PQ2620 for CH-1205 R130 24 1/4W D106 MBR20100CT A + 1 VAR101 471KD07 BEAD 1 BEAD C103 CX 0.47U/300V 12V 5A 5 3 R145 12K 1/4W D101 UF4005G C102 CY 2200P/250V L103 5UH 2 1 2 R134 4.
PAGE 82
13.AUDIO SCHEMATIC DIAGRAM OUT2- C1,C2,C4 --- 1uF/50V 12 GND 11 10 OUT2+ Volume 9 Vin2 8 GND 7 Vin1 6 Stand-by 5 OUT14 3 2 1 GND OUT1+ AN7522 VCC U1 J1 GND C3 2200uF/25V + + GND C1 1uF GND + 1 2 C2 1uF CON2 R1 10K R2 10K + C4 1uF GND R3 + 33K R4 68K R5 GND GND 15K C5 10uF/50V GND R6 GND 15K 5 4 3 2 1 C6 0.047uF R8 3K C7 0.