User Guide

Award BIOS
3-12
Chipset Features Refresh Cycle Time (us)
Refresh Cycle Time
(us)
15.6
62.4
124.8
187.2
This option lets you set the cycle time for the chipset
to refresh DRAM to avoid losing data.
Chipset Features RAS Pulse Width (Refresh)
RAS Pulse Width
(Refresh)
3T
4T
5T
6T
This parameter specifies the number of clocks
required to assert the DRAM row address strobe
(RAS) signal for refresh cycles.
Chipset Features RAS Precharge Time
RAS Precharge Time
2T
3T
4T
This parameter specifies the number of clocks
required to deassert the RAS signal to prevent DRAM
from losing data after performing a read.
Chipset Features RAS to CAS Delay
RAS to CAS Delay
2T
3T
4T
This option allows you to set the wait state between
the start of RAS and column address strobe (CAS)
signals. The available settings are. To calculate the
exact ISA bus clock, take the PCICLK/3 setting as an
example. For a 66MHz CPU with 33MHz PCI bus
clock, the ISA bus clock is calculated as follows:
33MHz/4 = 8.25MHz.