User Guide

AWARD BIOS
3-13
Chipset Features à Auto Configuration
Auto Configuration
Enabled
Disabled
When Enabled, the DRAM and cache related timing
are set to pre-defined value according to CPU type
and clock. Select Disable if you want to specify your
own DRAM timing.
Chipset Features à DRAM Timing
DRAM Timing
60 ns
70 ns
There to sets of DRAM timing parameters can be
automatically set by BIOS, 60ns and 70ns.
Warning: The default memory timing setting is
60ns to get the optimal performance. Because
the specification limitation of INTEL TX chipset
, 70ns SIMM can only be used with CPU
external clock 60MHz. To use 70ns SIMM with
66MHz CPU external clock may result in
unstable system behavior.
Chipset Features à DRAM Leadoff Timing
DRAM Leadoff
Timing
11/7/3/4
10/6/3/3
11/7/4/4
10/6/4/3
The Leadoff means the timing of first memory cycle in
the burst read or write. Actually, this item controls only
page miss read/write leadoff timing and the clocks of
RAS precharge and RAS to CAS delay. The four
digital represent Read Leadoff/ Write Leadoff/ RAS
Precharge/ RAS to CAS delay. For example, default is
10/6/3/3, which means you have 10-x-x-x DRAM page
miss read and 6-x-x-x DRAM write, with 3 clocks RAS
precharge and 3 clocks RAS to CAS delay.
Chipset Features à DRAM Read Burst (EDO/FP)