User Guide

AWARD BIOS
3-14
Chipset Features à DRAM Page Idle Timer
DRAM Page Idle
Timer
2 Clks
4 Clks
6 Clks
8 Clks
¦¹¿ï¶µ¥i³]©w CPU idle «á, DRAM page window ¥²¶·µ¥
«Ý´X-Óclock ¤~Ãö³¬¡C
Chipset Features à DRAM Enhance Paging
DRAM Enhance
Paging
Enabled
Disabled
³]©w¦¹¿ï¶µ¥\¯à¡A¥i¨Ï TX ´¹¤ù¨Ì¯S©wªº¤èªk¾¨¥i¯àºû
«ù DRAM page window ¥´¶}¡C
Chipset Features à SDRAM(CAS Lat/RAS-to-CAS)
SDRAM(CAS
Lat/RAS-to-CAS)
2/2
3/3
¦¹¿ï¶µ¥i³]©w SDRAM CAS Latency ©MRAS to CAS
delay¡C³o¨Ç³]©w-È¥i¼vÅT SDRAM ªº°õ¦æ³t«×¡A¹w³]-È
¬° 2 clock¡A¦pªG¦w¸Ë«á¡ASDRAM ¦³¤£¬Û®eªº±¡§Î¡A½Ð
±N2/2 §ï¬° 3/3¡C
Chipset Features à SDRAM Speculative Read
SDRAM Speculative
Read
Enabled
Disabled
¦¹¿ï¶µ¥i´î¤Ö 1 -Ó clock ªº SDRAM Leadoff Timing ªº
Ū¨ú®É¶¡¡C ¨ä°µªk¬°SDRAM read cycle ¦b¥¼³Q¸Ñ½X«e
¥ý°½¶]°e¨ì SDRAM ¤W, ¦pªG¦³¤@-Ó¥H¤WªºDIMM ¦w¸Ë
¦b¨t²Î¤W¡A¥²¶·±N°Ñ¼Æ-ȳ]¬°Disabled¡C
Chipset Features à System BIOS Cacheable
System BIOS
Cacheable
Enabled
Disabled
¦¹¿ï¶µ¤¹³\¨t²Î BIOS ³Q©ñ¤J§Ö¨ú°O¾ÐÅ餺
(Cacheable)¡A¥[³t¨t²Îªº°õ¦æ³t«×¡C