User Guide

AMI BIOS Utility
3-14
REFRESH RAS# ASSERTION
This function controls the number of clocks required to assert RAS# for
refresh cycles. The available settings are 4 clocks and 5 clocks.
FAST EDO PATH SELECT
Enable this option to select a fast path for CPU to DRAM read cycles to
minimize the lead-off time. This is applicable only for EDO DRAMs. For other
DRAM types, we recommend that you set this to Disabled.
SDRAM CAS# LATENCY
This parameter controls the wait state between SDRAM row address strobe
and SDRAM CAS signals.
SDRAM RAS# TIMING
This parameter controls the RAS# precharge, RAS# active-to-precharge time,
and refresh-to-RAS# active signal delay.
8-bit I/O Recovery Time (Sysclk)
This parameter allows you to set the response time of the 8-bit I/O devices
connected to your system. The settings range from 1-8 SYSCLK and
Disabled.
16-bit I/O Recovery Time (Sysclk)
This parameter allows you to set the response time of the 16-bit I/O devices
connected to your system. The settings range from 1-4 SYSCLK and
Disabled.
ISA Clock Divisor
This option specifies the ISA bus clock divisor. The selections are
PCICLK/4 and PCICLK/3.
Peer Concurrency
Enable the parameter to allow the CPU to run secondary DRAM PCI master
cycles to target PCI peer devices. Select Disabled to hold the CPU bus.
The default setting is Disabled.