User Guide

AWARD BIOS
3-12
Chipset Features Auto Configuration
Auto Configuration
Enabled
Disabled
When Enabled, the DRAM and cache related timing
are set to pre-defined value according to CPU type
and clock. Select Disable if you want to specify your
own DRAM timing.
Chipset Features DRAM Timing
DRAM Timing
60 ns
70 ns
There are two sets of DRAM timing parameters can
be automatically set by BIOS, 60ns and 70ns.
Warning: The default memory timing setting is
60ns to get the optimal performance. Because
the specification limitation of chipset, 70ns
SIMM can only be used with CPU external
clock 60MHz. To use 70ns SIMM with 66MHz
CPU external clock may result in unstable
system behavior.
Chipset Features DRAM Read Burst (EDO/FP)
DRAM Read Burst
(EDO/FP)
x444/x444
x333/x444
x222/x333
Read Burst means to read four continuous memory
cycles on four predefined addresses from the DRAM.
The default value is x222/x333 for 60ns EDO or FPM
(Fast Page Mode) DRAM. Which means the 2nd,3rd
and 4th memory cycles are 2 CPU clocks for EDO
and 3 clocks for FPM. The value of x is the timing of
first memory cycle and depends on the "DRAM Fast
Leadoff" setting.
Chipset Features DRAM Write Burst (EDO/FP)