User Guide

AWARD BIOS
3-13
DRAM Write Burst
(EDO/FP)
x444/x444
x333/x444
x333/x333
x222/x333
Write Burst means to write four continuous memory
cycles on four predefined addresses to the DRAM.
The default value is x222/x333 for 60ns EDO or FPM
(Fast Page Mode) DRAM. Which means the 2nd,3rd
and 4th memory cycles are 2 CPU clocks for EDO
and 3 clocks for FPM. The value of x is the timing of
first memory cycle and depends on the "DRAM Fast
Leadoff" setting.
Chipset Features DRAM Fast Leadoff
DRAM Fast Leadoff
Enabled
Disabled
This item enable or disable the DRAM Fast Leadoff
Timing. If enabled, the first cycle is 7 clocks. If
disabled, the first cycle is 8 clocks. The default must
be Disabled.
Chipset Features DRAM RAS# Precharge Time
DRAM RAS
Prechatge Time
3
4
The RAS Precharge means the timing to inactive RAS
and the timing for DRAM to do precharge before next
RAS can be issued. RAS is the address latch control
signal of DRAM row address. The default is 3 clocks
for 60ns EDO.
Chipset Features MA Additional Wait State
MA Additional Wait
State
Disabled
Enabled
To enable or disable one additional MA (DRAM
memory address) wait state. The default is Disabled.
Enable it if you have heavy loading (many chip count)
or lower speed DRAM.
Chipset Features RAS# to CAS# Delay
RAS# to CAS# Delay
Disabled
Enabled
To enable or disable additional RAS# to CAS# delay.
The default is Disabled for 60ns DRAM. Enable it if
you have heavy loading (many chip count) or 70ns
DRAM.