User Guide

AWARD BIOS
3-14
Chipset Features DRAM Refresh Queue
DRAM Refresh
Queue
Disabled
Enabled
This item enable or disable the 4-deep refresh queue
of refresh request. If Enabled, all refresh requests are
queued.
Chipset Features DRAM RAS Only Refresh
DRAM RAS Only
Refresh
Disabled
Enabled
This item determines the DRAM refresh type. There
are RAS-Only and CAS-before-RAS. The default is
Disabled, that is, CAS-before-RAS refresh.
Chipset Features Fast DRAM Refresh
Fast DRAM Refresh
Disabled
Enabled
This item determines the DRAM refresh rate, it should
be default Disabled, a faster DRAM refresh rate may
slightly reduce performance. If you find your old
DRAM is unstable, set this item to Enabled.
Chipset Features DRAM ECC/Parity Selection
DRAM ECC/Parity
Selection
Parity
ECC
Disabled
There are three modes of memory error detection or
correction, Parity mode, ECC mode and Disable. For
detail, please refer to section "Configuring the System
memory" in chapter 2.
Chipset Features ISA Bus Clock
ISA Bus Clock
PCICLK/4
PCICLK/3
This item selects the ISA bus clock. The PCI bus
clock is the CPU bus (external) clock divided by 2,
PCICLK= CPUCLK/2. For example, CPUCLK=66MHz,
PCICLK= 66/2=33MHz, ISA bus CLK=33/4=8.25MHz.