User Guide

AWARD BIOS
3-15
Chipset Features PCI Burst Write Combine
PCI Burst Write
Combine
Enabled
Disabled
If Enabled, the back-to-back sequential CPU to PCI
rite cycles are combined together as a single burst
write. Disable it, if you find any PCI card compatibility
problem.
Chipset Features PCI-to-DRAM Pipeline
PCI-to-DRAM
Pipeline
Enabled
Disabled
To enable or disable PCI to DRAM pipeline cycle. The
write cycles will be queued in the FIFO or buffer, and
CPU can be released to do next job.
Chipset Features CPU-to-PCI Write Post
CPU-to-PCI Write
Post
Enabled
Disabled
To enable or disable CPU to PCI bus post write cycle.
The write cycles will be queued in the FIFO or buffer,
and CPU can be released to do next job.
Chipset Features CPU-to-PCI IDE Posting
CPU-to-PCI IDE
Posting
Enabled
Disabled
To enable or disable CPU to PCI IDE post write cycle.
The IDE write cycles will be queued in the FIFO or
buffer, and CPU can be released to do next job.
Disable it, if you find any IDE compatibility problem.
Chipset Features Read-Around-Write
Read-Around-Write
Enabled
Disabled
If Disabled, all posted write are retired before a CPU
or PCI read access can be serviced. Disable it, if you
find any PCI card compatibility problem.