User Guide
Table Of Contents
- MX4GR
- Hardware Installation
- About “Optional” and “Upgrade Optional”…
- JP14 Clear CMOS Data
- CPU Installation
- CPU Jumper-less Design
- Full-range Auto-Detect CPU Core Voltage
- CPU and System Fan Connector (with H/W Monitoring)
- JP28 Keyboard/Mouse Wake-up Enable/Disable Jumper
- DIMM Sockets
- Front Panel Connector
- ATX Power Connector
- AC Power Auto Recovery
- IDE and Floppy Connector
- IrDA Connector
- S/PDIF (Sony/Philips Digital Interface) Connector
- AGP (Accelerated Graphic Port) Expansion Slot
- AGP Protection Technology
- ADD Card (Intel 845G chipset supported)
- WOM (Zero Voltage Wake on Modem) Connector
- WOM by External BOX Modem
- WOM by Internal Modem Card
- WOL (Wake on LAN)
- CNR (Communication and Network Riser) Expansion Slot
- PC99 Color Coded Back Panel
- Support 10/100 Mbps LAN onboard
- Support 2nd and 3rd USB2.0 Ports
- Chassis Intrusion Connector
- CD Audio Connector
- AUX-IN Connector
- Front Audio Connector
- Battery-less and Long Life Design
- CPU Over-current Protection
- Hardware Monitoring
- Resettable Fuse
- 2200μF Low ESR Capacitor
- Layout (Frequency Isolation Wall)
- Enlarged Aluminum Heatsink
- Driver and Utility
- Auto-run Menu from Bonus CD Disc
- Installing IntelR Chipset Software Installation Utility
- Intel Brookdale-G VGA driver
- Installing Intel IAA Driver
- Installing Onboard Sound Driver
- Installing LAN Driver
- Installing USB2.0 Driver
- Installing Hardware Monitoring Utility
- ACPI Suspend to Hard Drive
- ACPI Suspend to RAM (STR)
- Phoenix-AWARD BIOS
- Overclocking
- Glossary
- AC97
- ACPI (Advanced Configuration & Power Interface)
- AGP (Accelerated Graphic Port)
- AMR (Audio/Modem Riser)
- AOpen Bonus Pack CD
- APM (Advanced Power Management)
- ATA (AT Attachment)
- ATA/66
- ATA/100
- ATA/133
- BIOS (Basic Input/Output System)
- Bus Master IDE (DMA mode)
- CNR (Communication and Networking Riser)
- CODEC (Coding and Decoding)
- DDR (Double Data Rated) SDRAM
- DIMM (Dual In Line Memory Module)
- DMA (Direct Memory Access)
- ECC (Error Checking and Correction)
- EDO (Extended Data Output) Memory
- EEPROM (Electronic Erasable Programmable ROM)
- EPROM (Erasable Programmable ROM)
- EV6 Bus
- FCC DoC (Declaration of Conformity)
- FC-PGA (Flip Chip-Pin Grid Array)
- Flash ROM
- FSB (Front Side Bus) Clock
- I2C Bus
- IEEE 1394
- Parity Bit
- PBSRAM (Pipelined Burst SRAM)
- PC-100 DIMM
- PC-133 DIMM
- PC-1600 or PC-2100 DDR DRAM
- PCI (Peripheral Component Interface) Bus
- PDF Format
- PnP (Plug and Play)
- POST (Power-On Self Test)
- RDRAM (Rambus DRAM)
- RIMM (Rambus Inline Memory Module)
- SDRAM (Synchronous DRAM)
- Shadow E2PROM
- SIMM (Single In Line Memory Module)
- SMBus (System Management Bus)
- SPD (Serial Presence Detect)
- Ultra DMA
- USB (Universal Serial Bus)
- VCM (Virtual Channel Memory)
- ZIP file
- 102-108.pdf
- MX46LS
- Hardware Installation
- About “Optional” and “Upgrade Optional”…
- JP14 Clear CMOS Data
- CPU Installation
- CPU Jumper-less Design
- CPU and System Fan Connector (with H/W Monitoring)
- JP28 USB Keyboard / Mouse Wakeup
- DIMM Sockets
- Front Panel Connector
- ATX Power Connector
- AC Power Auto Recovery
- IDE and Floppy Connector
- IrDA Connector
- AGP (Accelerated Graphic Port) Expansion Slot
- WOM (Zero Voltage Wake on Modem) Connector
- WOM by External BOX Modem
- WOM by Internal Modem Card
- WOL (Wake on LAN)
- Support 10/100 Mbps LAN onboard
- CNR (Communication and Network Riser) Expansion Slot
- PC99 Color Coded Back Panel
- Support 3 USB Ports
- CD Audio Connector
- Modem Audio Connector
- Front Audio Connector
- Dr. LED Connector (Upgrade Optional)
- Battery-less and Long Life Design
- Over-current Protection
- Hardware Monitoring
- Resettable Fuse
- 1500μF Low ESR Capacitor
- Layout (Frequency Isolation Wall)
- Pure Aluminum Heatsink
- Driver and Utility
- AWARD BIOS
- Overclocking
- Glossary
- AC97
- ACPI (Advanced Configuration & Power Interface)
- AGP (Accelerated Graphic Port)
- AMR (Audio/Modem Riser)
- Bonus Pack CD
- APM (Advanced Power Management)
- ATA (AT Attachment)
- ATA/66
- ATA/100
- BIOS (Basic Input/Output System)
- Bus Master IDE (DMA mode)
- CNR (Communication and Networking Riser)
- CODEC (Coding and Decoding)
- DDR (Double Data Rated) SDRAM
- DIMM (Dual In Line Memory Module)
- DMA (Direct Memory Access)
- ECC (Error Checking and Correction)
- EDO (Extended Data Output) Memory
- EEPROM (Electronic Erasable Programmable ROM)
- EPROM (Erasable Programmable ROM)
- EV6 Bus
- FCC DoC (Declaration of Conformity)
- FC-PGA (Flip Chip-Pin Grid Array)
- Flash ROM
- FSB (Front Side Bus) Clock
- I2C Bus
- IEEE 1394
- Parity Bit
- PBSRAM (Pipelined Burst SRAM)
- PC-100 DIMM
- PC-133 DIMM
- PC-1600 or PC-2100 DDR DRAM
- PCI (Peripheral Component Interface) Bus
- PDF Format
- PnP (Plug and Play)
- POST (Power-On Self Test)
- RDRAM (Rambus DRAM)
- RIMM (Rambus Inline Memory Module)
- SDRAM (Synchronous DRAM)
- Shadow E2PROM
- SIMM (Single In Line Memory Module)
- SMBus (System Management Bus)
- SPD (Serial Presence Detect)
- Ultra DMA
- USB (Universal Serial Bus)
- VCM (Virtual Channel Memory)
- ZIP file
- Troubleshooting
- Technical Support
- Product Registration
- How to Contact Us

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DIMM socket has total 168-pin and supports 64-bit data. It can be single or double side, the golden finger signals on each side
of PCB are different, and that is why it was called Dual In Line. Almost all DIMMs are made by SDRAM
, which operate at 3.3V.
Note that some old DIMMs are made by FPM/EDO
and only operate at 5V. Do not confuse them with SDRAM DIMM.
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Channel for communications between the memory and surrounding devices.
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The ECC mode needs 8 ECC bits for 64-bit data. Each time memory is accessed; ECC bits are updated and checked by a
special algorithm. The ECC algorithm has the ability to detect double-bit error and automatically correct single-bit error while
parity mode can only detect single-bit error.
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The EDO DRAM technology is actually very similar to FPM (Fast Page Mode). Unlike traditional FPM that tri-states the memory
output data to start the pre-charge activity, EDO DRAM holds the memory data valid until the next memory access cycle, that is
similar to pipeline effect and reduces one clock state.
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