PowerPC G5 The World’s First 64-Bit Desktop Processor White Paper July 2003
White Paper PowerPC G5 Contents Page 3 Introduction Page 4 The World’s First 64-Bit Desktop Processor An Exponential Leap in Computing Power Memory Addressing up to 18 Exabytes High-Precision Calculations in a Single Clock Cycle Clock Speeds up to 2GHz Industry-Leading 1GHz Frontside Bus Full Support for Symmetric Multiprocessing Native Compatibility with 32-Bit Application Code Page 7 Next-Generation PowerPC Architecture Ultrafast Access to Data and Instructions Highly Parallel Execution Core Aggres
White Paper PowerPC G5 3 Introduction Key Features • 64-bit architecture, capable of addressing 18 exabytes of memory • Clock speeds up to 2GHz • 1GHz frontside bus for throughput of up to 8 GBps per processor • Dual independent 1GHz frontside buses in dual processor systems • Superscalar execution core supporting up to 215 in-flight instructions • Velocity Engine for accelerated singleinstruction, multiple-data (SIMD) processing • Two double-precision floating-point units for high-speed advanced computa
White Paper PowerPC G5 4 The World’s First 64-Bit Desktop Processor ND 32-bit processing Postcard = 24 in.2 (155 cm2) The PowerPC G5 marks the arrival of 64-bit performance to the personal computer market. With 64-bit-wide data paths and registers, this groundbreaking new processor can address vast amounts of main memory and handle multiple large integer and floating-point math calculations in a single clock cycle. An Exponential Leap in Computing Power 64-bit processing Manhattan = 22 mi.
White Paper PowerPC G5 5 High-Precision Calculations in a Single Clock Cycle With 64-bit-wide data paths and registers, the PowerPC G5 can execute instructions on 64 bits of data in a single clock cycle—making it possible to perform huge integer calculations and highly precise floating-point mathematics. In contrast, a 32-bit processor would have to split up any data larger than 32 bits and process it over multiple clock cycles.
White Paper PowerPC G5 6 Native Compatibility with 32-Bit Application Code On other platforms, switching to a 64-bit computer requires migrating to a 64-bit operating system (and purchasing 64-bit applications) or running a 32-bit operating system in a slow emulation mode.
White Paper PowerPC G5 7 Next-Generation PowerPC Architecture The PowerPC G5 is a highly parallel implementation of the PowerPC architecture, capable of handling multiple assorted tasks at the same time. It’s based on the execution core of IBM’s 64-bit POWER4 processor—recipient of the Microprocessor Report’s 2001 Analyst’s Choice Award for Best Workstation/Server Processor, which recognizes excellence in semiconductor technology innovation, design, and implementation.
White Paper PowerPC G5 8 PowerPC G5 Architecture Highly Parallel Execution Core Up to 215 in-flight instructions A wide architecture with 12 discrete processing units enables the PowerPC G5 to contain up to 215 in-flight instructions simultaneously— 71 percent more than the 126 instructions in a Pentium 4.
White Paper PowerPC G5 9 Optimized 128-Bit Velocity Engine 32-bit Processor 128-bit Velocity Engine The Velocity Engine can manipulate 128 bits of data at a time, up to four times faster than the general processing units in 32-bit processors. The PowerPC G5 uses a dual-pipelined Velocity Engine optimized with two independent queues and dedicated 128-bit registers and data paths for efficient instruction and data flow.
White Paper PowerPC G5 10 Condition Register This special 32-bit register summarizes the states of the floating-point and integer units. The condition register also indicates the results of comparison operations and provides a means for testing them as branch conditions. By bridging information between the branch unit and other functional units, the condition register improves the flow of data throughout the execution core.
White Paper PowerPC G5 11 Industry-Leading Performance Ultrafast clock speeds and a highly parallel 64-bit architecture make the PowerPC G5 ideal for next-generation multimedia, graphics, and scientific applications. Integer and floating-point math calculations are faster than ever thanks to 64-bit-wide registers and data paths.
White Paper PowerPC G5 12 SPECint_base2000 and SPECfp_base2000 measure the speed of a single task—either an integer calculation or a floating-point calculation—executing on a single processor. Each test measures how long the processor takes to complete the benchmark set of single tasks relative to a SPEC-defined baseline score. SPECint_base2000 is composed of eleven C and one C++ benchmark applications, including a chess program, a data compression utility, and a place-and-route simulator.
White Paper PowerPC G5 13 For comparisons that more accurately demonstrate the performance of a dual processor system, VeriTest used the “SPEC rate” metrics, which recognize multiple processors. With SPECint_rate_base2000 and SPECfp_rate_base2000, the benchmark code is compiled and multiple copies are run concurrently, allowing both processors to work in parallel. SPEC rate tests determine the number of times a system can complete the benchmark per hour, also referred to as system throughput.
White Paper PowerPC G5 Technical Specifications 64-bit PowerPC processor architecture Virtual address range: 64 bits, or 18 exabytes Physical address range: 42 bits, or 4 terabytes Full 64-bit data paths and registers Native support for 32-bit application code 64K L1 instruction cache; 32K L1 data cache 512K internal L2 cache Dedicated data flow for dividing one instruction into two internal operations Microcoded instructions for up to four internal operations Support for up to eight outstanding L1 cache
White Paper PowerPC G5 • • • • • • Three-component branch prediction logic Speculative superscalar inner core organization Fast, selective flush of incorrect speculative instructions and results Prediction of up to two branches per cycle Support for up to 16 predicted branches in flight Prediction hints added to branch instructions Prediction support for branch direction and branch addresses Physical specifications • 58 million transistors • 130-nanometer, silicon-on-insulator (SOI) process • Die size: 1
