Xserve G5 Developer Note 2005-01-04
Apple Inc. © 2002, 2005 Apple Computer, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, mechanical, electronic, photocopying, recording, or otherwise, without prior written permission of Apple Inc.
Contents Introduction Introduction to Xserve G5 Developer Note 9 Organization of This Document 9 Chapter 1 Overview of the Xserve G5 11 Hardware Features 11 Features of the Enclosure 13 System Activity Lights Definitions 15 System Software 16 Server Software Features 16 Security Features 17 Storage Support 17 Management Support 18 Computer Feature Identification 18 Velocity Engine Acceleration 19 Chapter 2 Architecture 21 Block Diagram and Buses 21 Processor Module 23 PowerPC G5 Microprocessor 23 Cache
C O N T E N T S Power Controller 28 Dual System Monitor ICs 28 System Activity Lights 28 Device Identification 28 Optional Graphics Card 29 Input and Output Devices 31 Chapter 3 USB Ports 31 USB Connectors 31 FireWire Ports 32 FireWire 800 Connector 33 FireWire 400 Connector 34 Booting from a FireWire Device 35 Ethernet Ports 35 Serial Port 36 Disk Drives 37 Combo Drive 37 SuperDrive (Optional) 38 Hard Disk Drives 38 VGA Connector 39 Expansion 41 Chapter 4 RAM Expansion 41 DIMM Specifications 41 DIMM
C O N T E N T S Serial Interface Standards 49 Appendix B Conventions and Abbreviations 51 Typographical Conventions 51 Abbreviations 51 Index 55 5 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
C O N T E N T S 6 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
Figures and Tables Chapter 1 Overview of the Xserve G5 11 Figure 1-1 Figure 1-2 Figure 1-3 Table 1-1 Table 1-2 Table 1-3 Chapter 2 Architecture 21 Figure 2-1 Chapter 3 Simplified block diagram 22 Input and Output Devices 31 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Chapter 4 Xserve G5 slot load front panel 14 Xserve G5 slot load and cluster node back panel 15 Xserve G5 cluster node front panel 15
F I G U R E S A N D T A B L E S 8 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
I N T R O D U C T I O N Introduction to Xserve G5 Developer Note This developer note describes Apple Computer’s Xserve G5. The note provides information about the internal design of the computer, its input-output and expansion capabilities, and issues affecting compatibility. This developer note is intended to help hardware and software developers design products that are compatible with the Macintosh products described here.
I N T R O D U C T I O N Introduction to Xserve G5 Developer Note 10 Organization of This Document 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
C H A P T E R 1 Overview of the Xserve G5 The Xserve G5 is the Macintosh server platform using the PowerPC G5 microprocessor. It has a rack-mount enclosure and includes server-oriented features such as ample internal storage, hot-pluggable drives, hardware monitoring, and easy tool access. This developer note includes both the standard three drive bay configuration and the basic cluster node single drive bay configuration.
C H A P T E R 1 Overview of the Xserve G5 Additional Features Hyper Transport A high-speed bus architecture between the memory controller and device I/O. For more information, see “HyperTransport Technology” (page 25). Processor system bus 64-bit processor interface bus running at half the speed of the system microprocessor. See “Processor Bus” (page 24). Memory caches Internal 512 KB level 2 cache per processor. See “Cache Memory” (page 23). ROM ROM-in-RAM implementation with 2 MB of boot ROM.
C H A P T E R 1 Overview of the Xserve G5 Hyper Transport A high-speed bus architecture between the memory controller and device I/O. For more information, see “HyperTransport Technology” (page 25) ROM ROM-in-RAM implementation with 2 MB of boot ROM. For information about the ROM, see “Boot ROM” (page 27). For information about the ROM-in-RAM implementation, see the references listed in “ROM-in-RAM Architecture” (page 46).
C H A P T E R 1 Overview of the Xserve G5 Note: Depending on the configuration of your Xserve G5, the appearance may differ slightly from the illustrations.
C H A P T E R 1 Overview of the Xserve G5 Figure 1-2 Xserve G5 slot load and cluster node back panel Gigabit Ethernet port(s) Power socket Ethernet activity lights PCI-X card expansion slots (2) USB ports (2) Ethernet link lights System identifier button/light FireWire 800 ports (2) Serial console port Figure 1-3 (page 15) shows the front panel of the cluster node Xserve G5, which has a power button and light, an enclosure lock and status light, a system identifier button and light, a FireWire 400
C H A P T E R 1 Overview of the Xserve G5 The bottom row of system activity lights on the Xserve G5 (shown in Figure 1-1 (page 14) and Figure 1-3 (page 15) indicates the state of the computer when commands are entered and during normal operation. The lights are referenced from right to left, with light one being the rightmost and light 8 being the leftmost. The bottom row of system activity lights are defined below in Table 1-3.
C H A P T E R 1 Overview of the Xserve G5 An editable UPS shutdown script that will run when the machine powers down because of UPS is available in the /user/libexec/upsshutdown directory. ■ Auto restart after power failure: Xserve G5 hardware supports auto restart after power failure through software control. In the event of a power outage, an Xserve G5 unit detects the return of power and performs an automatic restart.
C H A P T E R 1 Overview of the Xserve G5 man diskutil ■ Remote volume configuration: The system software can remotely configure newly mounted volumes. ■ USB and FireWire alerts: Xserve G5’s keyswitch security prevents unauthorized hot-plugging and mounting of a USB or FireWire hard drive. When the keyswitch is locked, the CD is ejected. In addition, the Security System pane provides configuration support for USB keyboard and mouse.
C H A P T E R 1 Overview of the Xserve G5 For both Xserve G5 configurations, the value of the model property is RackMac3,1. Velocity Engine Acceleration The Velocity Engine (an implementation of AltiVec) is the vector processing unit in the PowerPC G5 microprocessor. Some system software has been modified to take advantage of the accelerated processing that the Velocity Engine makes possible. System software has also been modified to support low-level operations using the Velocity Engine.
C H A P T E R 1 Overview of the Xserve G5 20 System Software 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
C H A P T E R 2 Architecture This chapter describes the architecture of the Xserve G5. It includes information about the major components on the logic boards: the microprocessor, the other main ICs, and the buses that connect them to each other and to the I/O interfaces. Block Diagram and Buses The architecture of Xserve G5 is based on one or two PowerPC G5 microprocessors and two custom ICs: the U3H memory controller and bus bridge and the K2 I/O controller.
C H A P T E R 2 Architecture Figure 2-1 Simplified block diagram Processor module Processor module 64-bit PowerPC G5 microprocessor 64-bit PowerPC G5 microprocessor Processor interface bus running at half the processor speed Main logic board DIMM slots 400 MHz ECC DDR memory bus U3H memory controller and PCI bus bridge 16-bit 4.
C H A P T E R 2 Architecture ■ Internal PCI bus: 33 MHz, 32-bit bus supports the K2 I/O controller, the boot ROM, and the USB controllers ■ Serial ATA (SATA) bus: supports 1.5 Gbps internal hard drive connectors ■ Ultra DMA ATA/100 bus: support internal optical drive, where available ■ HyperTransport: high-speed, bidirectional, point-to-point link for integrated circuits supports bidirectional data rates up to 4.8 GBps The remainder of this chapter describes the architecture of the Xserve G5.
C H A P T E R 2 Architecture Note: The Xserve G5 does not use jumpers to control the clock speeds of the processor and cache. Dual Processors The dual-processor configurations of the Xserve G5 have two processor cards containing a PowerPC G5 processor. The dual-processor configurations allow applications that support multitasking to about double their performance. Note: The cluster node Xserve G5 is available only in dual configuration.
C H A P T E R 2 Architecture HyperTransport Technology The DDR HyperTransport is an advanced chip-to-chip communications technology that provides a high-speed, high-performance, point-to-point link for integrated circuits. HyperTransport provides a universal connection that reduces the number of buses within a system. The HyperTransport bus between the U3H IC and the PCI-X bridge is 16 bits wide, supporting total of 4.8 GBps bidirectional throughput.
C H A P T E R 2 Architecture The U3H IC used in the Xserve G5 supports the PCI write combining feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. For memory write transactions to be combined, they must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands prevents any write combining.
C H A P T E R 2 Architecture Internal PCI Bus An internal 33-MHz, 64-bit PCI bus connects the K2 I/O controller to the boot ROM and the USB controller. The internal PCI bus offers no development opportunity. Boot ROM The boot ROM supports up to 2 MB of on-board flash EPROM. The boot ROM includes the hardware-specific code and tables needed to start up the computer.
C H A P T E R 2 Architecture FireWire Controllers The K2 IC includes a FireWire controller that supports both IEEE 1394b (FireWire 800) with a maximum data rate of 800 Mbps (100 MBps) and IEEE 1394a (FireWire 400) with a maximum data rate of 400 Mbps (50 MBps). The IC is backwards-compatible with 1394a (FireWire 400). The K2 IC provides DMA (direct memory access) support for the FireWire interface.
C H A P T E R 2 Architecture Optional Graphics Card The Xserve G5 has a build-to-order option of an ATI RV100 64 MB RAM VGA/PCI graphics card with a VGA connector. The ATI RV100 runs at 64-bit PCI 33 or 66 MHz. The Xserve G5 can boot headless (that is, without an attached monitor). While booted headlessly, the system actually creates a virtual display and draws into an off-screen buffer, without attempting to update a physical display.
C H A P T E R 2 Architecture 30 Optional Graphics Card 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
C H A P T E R 3 Input and Output Devices This chapter describes the Xserve G5’s built-in I/O devices and the ports for connecting external I/O devices. Each of the following sections describes an I/O port or device. USB Ports The Xserve G5 has two external Universal Serial Bus (USB) 2.0 ports. The USB ports are off of the USB controller connected to the PCI bus, bridged by K2. All USB ports are fully compliant with the USB 2.
C H A P T E R 3 Input and Output Devices Table 3-1 Signals on the USB connector Pin Signal name Description 1 VCC +5 VDC 2 D– Data – 3 D+ Data + 4 GND Ground The Xserve G5 provides power for the USB ports at 5 V and up to 500 mA on each port. The ports share the same power supply; a short circuit on one will disable both ports until the short has been removed. The USB ports support all USB 2.0 speeds: high-speed (480 Mbps) and classic USB speeds of full-speed (12 Mbps) and low-speed (1.
C H A P T E R 3 Input and Output Devices FireWire 800 Connector The FireWire 800 port on the Xserve G5 is based on IEEE 1394b and enables a 800 Mbps transfer rate. FireWire 800 uses a 9-pin connector and is backwards compatible with original 1394 FireWire devices with 6-pin or 4-pin connectors. With the appropriate cable, the 9-pin port works seamlessly with legacy FireWire devices. Cables are available to go from both 6-pin and 4-pin connectors to a 9-pin, and 9-pin to 9-pin.
C H A P T E R 3 Input and Output Devices The 9-pin FireWire port is capable of operating at 100, 200, 400, and 800 Mbps, depending on the device it is connected to. Using a cable with a 9-pin connector at one end and a 4-pin or 6-pin connector at the other, the 9-pin port is capable of directly connecting to all existing FireWire devices. Using a cable with 9-pin connectors at both ends, the 9-pin port is capable of operating at 800 Mbps.
C H A P T E R 3 Input and Output Devices The power pin provides up to 15 W total power for all three FireWire connectors. The voltage on the power pin can be from 18 to 25 V. Pin 2 of the FireWire 400 connector is ground return for both power and the inner cable shield. In a FireWire cable with a 4-pin connector on the other end, the wire from pin 2 is connected to the shell of the 4-pin connector.
C H A P T E R 3 Input and Output Devices Pin Signal name Signal definition 6 RXN Receive (negative lead) 7 – Not used 8 – Not used Table 3-5 Signals for 1000Base-T operation Pin Signal name Signal definition 1 TRD+(0) Transmit and receive data 0 (positive lead) 2 TRD–(0) Transmit and receive data 0 (negative lead) 3 TRD+(1) Transmit and receive data 1 (positive lead) 4 TRD+(2) Transmit and receive data 2 (positive lead) 5 TRD–(2) Transmit and receive data 2 (negative lead) 6
C H A P T E R 3 Input and Output Devices Figure 3-4 1 2 Serial port connector 3 7 6 Table 3-6 4 8 5 9 Serial port signals Pin Signal name Signal description 1 RLSD Received line signal detector 2 RD Received data 3 TD Transmitted data 4 DRT DTE ready 5 SGND Signal ground 6 DCR DCE ready 7 RTS Request to send 8 CTS Clear to send 9 RI Ring indicator (wake up system) Disk Drives The standard Xserve G5 has three bay modules supporting up to three internal hard disk drives
C H A P T E R 3 Input and Output Devices Media type Reading speed Writing speed CD-R 24x (CAV max) 24x (ZCLV) CD-RW 24x (ZCAV max) 16x (ZCLV, for Ultra speed media) CD or CD-ROM 24x (CAV max) – SuperDrive (Optional) The standard Xserve G5 supports an optional, slot-loading SuperDrive (combination DVD-R and CD-RW drive). The SuperDrive can read DVD media and read and write CD media, as shown in Table 3-8.
C H A P T E R 3 Input and Output Devices Note: Pin eleven supports the drive activity light. For full functionality of the drive activity light and system monitoring, use Apple drives. Other drives are not supported. The drives on the independent Serial ATA buses implement revision one ports. For references to SATA website information, refer to “Serial ATA” (page 48). Each drive carrier has two LEDs.
C H A P T E R 3 Input and Output Devices Pin Signal name 40 Description 7 GREEN_RTN Green video signal return 8 BLUE_RTN Blue video signal return 9 n.c. No connect 10 GND Ground 11 n.c. No connect 12 SDA I2C data 13 HSYNC Horizontal synchronization signal 14 VSYNC Vertical synchronization signal 15 SCL I2C clock VGA Connector 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
C H A P T E R 4 Expansion This chapter describes the RAM expansion slots and the PCI expansion slots of the Xserve G5. RAM Expansion The main logic board of the Xserve G5 has four pairs of ECC DDR SDRAM expansion slots for unregistered, unbuffered DDR400 (PC3200) dual in-line memory modules (DIMMs) for a maximum memory of 8 GB. The Xserve G5 has eight memory slots (in two banks for four each), at least two of which are filled at the factory.
C H A P T E R 4 Expansion The Serial Presence Detect (SPD) EEPROM specified in the JEDEC standard is required and must be set to properly define the DIMM configuration. The EEPROM is powered on 2.5V. Details about the required values for each byte on the SPD EEPROM can be found on pages 68–70 of the JEDEC specification. Important: For a DIMM to be recognized by the startup software, the Serial Presence Detect feature must be programmed properly to indicate the timing modes supported by the DIMM.
C H A P T E R 4 Expansion Table 4-2 Address multiplexing modes for ECC DDR SDRAM devices Device size Device configuration Size of row address Size of column address 128 Mbits 4Mx8x4 12 10 128 Mbits 2 M x 16 x 4 12 9 256 Mbits 8Mx8x4 13 10 256 Mbits 4 M x 16 x 4 13 9 512 Mbits 8Mx8x4 13 11 PCI and PCI-X Expansion Slots The Xserve G5 provides Bus A and Bus B via the HyperTransport bus.
C H A P T E R 4 Expansion 44 PCI and PCI-X Expansion Slots 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
A P P E N D I X A Supplemental Reference Documents For more information about the technologies mentioned in this developer note, you may wish to consult some of the references listed in the following sections. Apple Technical Notes Apple Technical Notes answer many specific questions about the operation of Macintosh computers and the Mac OS. The technical notes are available on the Technical Note website at http://developer.apple.
A P P E N D I X A Supplemental Reference Documents Mac OS X and Mac OS Server For access to Apple’s developer documentation for Mac OS X, see the website at http://developer.apple.com/documentation/MacOSX/MacOSX.html and http://developer.apple.com/documentation/Carbon/Reference/Multiprocessing_Services/ For information on Apple’s server documentation for Mac OS X, see the website at http://developer.apple.com/server/ O'Reilly & Associates publishes a series of books about Mac OS X development.
A P P E N D I X A Supplemental Reference Documents http://developer.apple.com/technotes/tn/tn1062.html TN 1044: Open Firmware, Part III, at http://developer.apple.com/technotes/tn/tn1044.html Other technical notes provide additional information about Open Firmware on the Macintosh. TN 2000: PCI Expansion ROMs and You, at http://developer.apple.com/technotes/tn/tn2000.html TN 2001: Running Files from a Hard Drive in Open Firmware, at http://developer.apple.com/technotes/tn/tn2001.
A P P E N D I X A Supplemental Reference Documents Serial ATA For information on Serial ATA specifications and design guides, go to the World Wide Web at http://www.serialata.org USB Interface For more information about USB on the Macintosh computer, refer to Apple Computer’s Accessing Hardware from Applications at http://developer.apple.com/documentation/HardwareDrivers/index.
A P P E N D I X A Supplemental Reference Documents Serial Interface Standards The Telecommunications Industry Association (TIA) is the trade organization that publishes the standards for the RS-232 serial interface. To obtain copies of the standards, you can contact the TIA’s web page at http://www.tiaonline.org/standards/ Serial Interface Standards 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
A P P E N D I X A Supplemental Reference Documents 50 Serial Interface Standards 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
A P P E N D I X B Conventions and Abbreviations This developer note uses the following typographical conventions and abbreviations. Typographical Conventions Note: A note like this contains information that is of interest but is not essential for an understanding of the text. Important: A note like this contains important information that you should read before proceeding. Abbreviations When unusual abbreviations appear in this developer note, the corresponding terms are also spelled out.
A P P E N D I X B Conventions and Abbreviations kg kilograms sec. seconds kHz kilohertz V volts k kilohms W watts lb.
A P P E N D I X B Conventions and Abbreviations IEEE Institute of Electrical and Electronics Engineers IEEE 1274 the official specification for Open Firmware IEEE 1394a the official specification for FireWire 400 IEEE 1394b the official specification for FireWire 800 IIC inter-IC (an internal control bus) IIS inter-IC sound bus I/O input/output ISO International Organization for Standardization JEDEC Joint Electronics Devices Engineering Council L2 level 2 (refers to level of cache) LAN
A P P E N D I X B Conventions and Abbreviations 54 ROM read-only memory RS-232 standard serial interface RS-422 standard serial interface SBP Serial Bus Protocol SPD Serial Presence Detect SCSI Small Computer System Interface SCC serial communications controller SNMP simple network management protocol SDRAM synchronous dynamic random access memory SRAM static random access memory UPS uninterruptible power supply USB Universal Serial Bus VRAM video RAM; used for display buffers
Index abbreviations 51–54 AltiVec 19 Apple PI elastic buses 24 VGA display connector 39 custom ICs K2 I/O controller 26 PMU99 power controller 28 U3H bridge and memory controller 24 USB controllers 27 B D block diagram 21 block diagrams main logic board 22 boot ROM 27 boot FireWire 35 headless 17, 29 booting from a FireWire device 35 buses 21 Apple PI elastic bus 24 memory bus 22, 24 PCI bus 23, 27 PCI-X bus 22, 25 processor bus 22, 24 DIMMs.
I N D E X G P G5, See PowerPC G5 microprocessor graphics support 25 PCI bus 23, 27, 43 PCI expansion slots 43 PCI write combining 26, 27 PCI-X bus 22, 25 PMU99 IC 28 power controller IC 28 PowerPC G5 microprocessor 23 presence detect feature of DIMMs 42 processor bus 22, 24 H HyperTransport 25 I I/O ports Ethernet 35 FireWire 32 video monitor 39 interrupts 26 K K2 I/O controller IC 26 R RAM DIMMs 41–42 capacities of 42 configurations 42 devices in 42 installation of 41 mechanical specifications of 4
I N D E X video monitor ports 39 VGA 39 W write combining 26, 27 57 2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
