User's Manual

SECTION THREE
THEORY OF OPERATION
3.0 GENERAL
The Model 1225 Hand Held Transceiver is a push-to-talk, spread spectrum
transceiver. It uses digitized audio. The digital data stream is scrambled
before modulation for security. The combination of spread spectrum modulation
and scrambled, digitized audio give the Model 1225 its low probability of
detection and interception characteristics.
3.1 FUNCTIONAL DESCRIPTION
The Model 1225 block diagram can be divided into two sections. The upper
half contains the digital and audio signal processing functions. The lower half
contains the IF and RF signal processing functions.
3.1.1 Audio/Digital Section
In the transmit direction, audio can come either from the internal
microphone in the Model 1225, or from an external speaker/microphone.
Microphone audio is amplified by the microphone pre-amplifier stage. This stage
also has an audio AGC (Automatic Gain Control) function that produces a constant
audio signal level for the CVSD (Continuously Variable Slope Delta-modulation)
encoder. The AGC has an attack time of less than 1ms and a decay time of 150
ms. A lowpass filter between the pre-amplifier and the encoder limits the audio
signal bandwidth to prevent aliasing.
CVSD encoding converts the analog audio into a serial data stream. The
bit rate of this data stream is equal to the CVSD clock signal frequency.
Processing of the serial data stream is performed by the FPGA (Field
Programmable Gate Array).
Serial data from the encoder is processed by the scrambler/ de-scrambler
in the FPGA. The scrambler/de-scrambler is a dual purpose block that is
switched between transmit and receive modes. In transmit mode, the encoder data
stream is combined with a pseudo-random key stream. The key stream is generated
from the scrambler key that is stored in the key memory. The scrambler key
manager monitors the status of the CODE signal. It then reads the appropriate
key from the key memory, and sends it to the scrambler/de-scrambler. The same
key is used for both transmitting and receiving.
Key memory programming access for the Model 1260 Key loader is provided
through the key loader input jack.
Once the data stream from the CVSD encoder is scrambled, it is ready to be
spread spectrum modulated. The PN (Pseudo-Noise) sequence generator produces a
long digital sequence, at a clock rate that is much greater than the signal from
the data scrambler. The PN sequence is combined with data scrambler signal by
the spread spectrum modulator. This produces the spread data signal, which,
along with the PN sequence, is bi-phase modulated by the clock signal from the
modulator clock generator. Further processing of these signals occurs outside
the FPGA.
Two clock generator circuits are included in the FPGA, both being driven
from the same crystal oscillator stage. The data clock generator has three
outputs: the PN clock, the scrambler clock and the CVSD clock. The modulator
clock generator has two outputs, one being twice the frequency of the other,
driving the bi-phase modulators.
In the receive direction, the FPGA demodulates the BPSK (binary phase
shift keyed) signal from the 2nd IF to recover the scrambled digital data. At
the same time, the lock detector determines when a valid system signal is
present, and controls the lock functions. .
The demodulator produces the baseband data signal, which is a scrambled
CVSD data stream. The descrambler removes the scrambler key stream from the