n ly O ly u tr r fo l a ti n e d fi n o PRELIMINARY SPECIFICATION 1/4" color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology OV5647 C datasheet
e d fi n o C a ti n l r fo ly u tr n ly O
i 00Copyright © 2009 OmniVision Technologies, Inc. All rights reserved. This document is provided “as is” with no warranties whatsoever, including any warranty of merchantability, n ly non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. OmniVision Technologies, Inc.
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
iii 00applications ordering information cellular phones OV05647-G04A (color, chip probing, 200 µm backgrinding, reconstructed wafer) n ly toys PC multimedia 00features 1.4 µm x 1.
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION
v 00table of contents 1-1 2 system level description 2-1 n ly 1 signal descriptions 2-1 2.2 architecture 2-1 O 2.1 overview 2.3 format and frame rate 2-3 2.4 I/O control 2-3 ly 2.4.1 system clock control 2.5 power up sequence u 2.5.1 power up with internal DVDD tr 2.5.2 power up with external DVDD source 2.6 reset r 2.7 standby and sleep fo 3 block level description 3.1 pixel array structure 3.2 binning l 3.3 analog amplifier n 4.1 mirror and flip 4.3.2 square d 4.3.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.6.2 LAEC 4-12 4.6.3 banding mode ON with AEC 4-12 4-12 4.6.5 auto gain control (AGC) 4-12 n ly 4.6.4 night mode 4.7 black level calibration (BLC) 4.8 strobe flash and frame exposure O 4.8.1 strobe flash control 4.9 xenon flash control 4.9.1 LED1 & 2 mode ly 4.9.2 LED 3 mode 4.10 frame exposure (FREX) mode 4.11 FREX strobe flash control tr u 4.10.1 FREX control 4.12 one-time programmable (OTP) memory 5.
vii 8.4 AC characteristics 8-3 9 mechanical specifications 9-1 9-1 n ly 9.1 physical specifications 10 optical specifications 10-1 10-1 10.2 lens chief ray angle (CRA) 10-2 C o n fi d e n ti a l fo r tr u ly O 10.1 sensor array center 11.03.
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
ix pad diagram 1-4 figure 2-1 OV5647 block diagram 2-1 figure 2-2 reference design schematic 2-2 figure 2-3 power up timing with internal DVDD 2-4 figure 2-4 power up timing with external DVDD source figure 3-1 sensor array region color filter layout figure 3-2 example of 2x2 binning figure 4-1 mirror and flip samples figure 4-2 image windowing figure 4-3 color bar types figure 4-4 color, black and white square bars figure 4-5 transparent effect figure 4-6 rolling bar effect fi
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
xi 00list of tables signal descriptions 1-1 n ly table 1-1 1-3 table 2-1 format and frame rate 2-3 table 3-1 horizontal and vertical binning registers 3-2 O table 1-2 pad configuration under various conditions table 4-1 mirror flip control registers 4-1 table 4-2 image windowing registers 4-2 ly table 4-3 test pattern registers table 4-4 50/60 Hz detection control registers u table 4-5 AEC/AGC control function registers tr table 4-6 average based control function registers table 4-7 ave
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-4 AEC/AGC 1 registers 7-8 table 7-5 system timing registers 7-8 7-11 n ly table 7-6 AEC/AGC 2 registers table 7-7 STROBE/frame exposure control registers table 7-8 50/60 HZ DETECTION registers table 7-9 OTP control registers O table 7-10 BLC registers table 7-11 frame control registers ly table 7-12 DVP registers table 7-13 MIPI top registers u table 7-14 ISPFC registers table 7-15 ISP TOP control registers tr
1-1 1 signal descriptions table 1-1 lists the signal descriptions and their corresponding pad numbers for the OV5647 image sensor. The die signal descriptions (sheet 1 of 2) O table 1-1 n ly information is shown in section 9. signal name pad type description 1 AVDD power power for analog circuit, 2.8V 2 AGND power ground for analog circuit 3 DOGND power ground for digital I/O 4 SCL input SCCB clock input 5 SDA I/O SCCB data I/O 6 DVDD power power for digital core circuit, 1.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology pad number signal name pad type 23 DVDD power power for digital core circuit, 1.5V (connect to 0.1uF capacitor to ground) 24 DOVDD power power for digital I/O, 1.7 ~ 3.0V 25 DOGND power ground for digital I/O 26 AVDD power power for analog circuit, 2.8V 27 HREF I/O DVP HREF output 28 PCLK I/O DVP PCLK output 29 VSYNC I/O DVP VSYNC output 30 DOVDD power power for digital I/O, 1.7 ~ 3.
1-3 table 1-2 pad configuration under various conditions RESETa RESETb post-RESET software sleep hardware standby (power down pin = 1) VSYNC high-z high-z input by default (configurable) high-z by default (configurable) high-z by default (configurable) HREF high-z high-z input by default (configurable) high-z by default (configurable) high-z by default (configurable) PCLK high-z high-z input by default (configurable) high-z by default (configurable) high-z by default (configurable)
e d fi n o C a ti n 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 DOVDD XCLK PVDD EGND D4/MDP1 D5/MDN1 EGND D6/MCP D7/MCN EVDD D8/MDP0 D9/MDN0 D3 D2 D1 D0 DOVDD VSYNC PCLK HREF AVDD DOGND DOVDD DVDD r fo 48 47 DOGND DVDD l 50 49 proprietary to OmniVision Technologies OV5647 ly u tr AGND 19 DOGND AVDD 18 22 DVDD n ly O RESETB 17 TM PWDN DVDD 15 16 21 DOVDD VREF2 VREF1 20 FREX 12 13 14 GPIO1 8 STROBE SGND 7 11 DVDD 6 GPIO0 DOGND SCL S
2-1 2 system level description n ly 2.1 overview The OV5647 is a low voltage, high performance, 5 megapixel CMOS image sensor that provides 2592x1944 video output using OmniBSI™ technology. It provides multiple resolution raw images via the control of the serial camera control bus O or MIPI interface. The OV5647 has an image array capable of operating up to 15 fps in 2592x1944 resolution with user control of image quality, data transfer, camera functions through the SCCB interface.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology figure 2-2 reference design schematic AVDD 2 19 50 3 21 25 48 40 DOVDD HREF U1 OV5647 BSI COB DOVDD PVDD PCLK RESETB EVDD PWDN SGND SCL AGND SDA AGND XCLK AGND VREF1 DOGND VREF2 DOGND FREX DOGND STROBE DOGND GPIO0 EGND GPIO1 EGND TM PCLK 17 31 D0 19 29 VSYNC 21 27 HREF 28 R6 17 RESETB 15 PWDN 4 SIOC 5 SIOD 45 XCLK 14 VREFH 13 D1 FREX STROBE 9 GPIO0 8 GPIO1 20 23 33-0
2-3 2.3 format and frame rate format and frame rate resolution frame rate scaling method pixel clock 5 Mpixel 2592x1944 15 fps full resolution 80 MHz 1080p 1920x1080 30 fps cropping 68 MHz 960p 1280x960 45 fps cropping, subsampling/ binning 91.2 MHz 720p 1280x720 60 fps cropping, subsampling/ binning 92 MHz VGA 640x480 90 fps cropping, subsampling/ binning QVGA 320x240 120 fps cropping, subsampling/ binning ly O format n ly table 2-1 46.5 MHz tr u 32.5 MHz 2.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology figure 2-3 power up timing with internal DVDD VDD_IO first, then VDD_A, and rising time is less than 5 ms n ly T0 VDD_IO (DOVDD) T2 O VDD_A (AVDD) power on period SCCB activity is okay during entire period u SCCB power down ly PWDN 5647_DS_2_3 tr note T0 ≥ 0 ms: delay from VDD_IO stable to VDD_A stable T2 ≥ 5 ms: delay from VDD_A stable to sensor power up stable 2.5.
2-5 figure 2-4 power up timing with external DVDD source T0 cut off power VDD_IO (DOVDD) T1 O VDD_A (AVDD) n ly VDD_IO first, then VDD_A, followed by VDD_D, and rising time is less than 5 ms T2 VDD_D (DVDD) ly power on period 5647_DS_2_4 fo note T0 ≥ 0 ms: delay from VDD_IO stable to VDD_A stable T1 ≥ 0 ms: delay from VDD_A stable to VDD_D stable T2 ≥ 5 ms: delay from VDD_D stable to sensor power up stable tr SCCB activity is okay during entire period r SCCB u PWDN 2.
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
3-1 3 block level description The OV5647 sensor has an image array of 2624 columns by 1956 rows (5,132,544 pixels). figure 3-1 shows a cross-section of the image sensor array. n ly 3.1 pixel array structure O The color filters are arranged in a Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion. Of the 5,132,544 pixels, 5,038,848 (2592x1944) are active pixels and can be output. The other pixels are used for black level calibration and interpolation.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 3.2 binning The OV5647 supports 2x2 binning for better SNR in low light conditions. See table 3-1 for horizontal and vertical binning table 3-1 n ly registers.
4-1 4 image sensor core digital functions The OV5647 provides mirror and flip read-out modes, which respectively reverse the sensor data read-out order n ly 4.1 mirror and flip horizontally and vertically (see figure 4-1).
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.2 image windowing An image windowing area is defined by four parameters, x_addr_start, x_addr_end, y_addr_start, y_addr_end. By n ly properly setting the parameters, any portion or size within the sensor array can be defined as an visible area. This windowing is achieved by simply masking the pixels outside the defined window; thus, it will not affect the original timing.
4-3 4.3 test pattern For testing purposes, the OV5647 offers three types of test patterns, color bar, square and random data.The OV5647 n ly also offers two effects: transparent effect and rolling bar effect. The output type of test pattern is controlled by register 0x503D[1:0] register (test_pattern_type). 4.3.1 color bar O There are four types of color bars shown in figure 4-3. The output type of color the color bar can be selected by bar style register 0x503D[3:2].
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.3.3 random data There are two types of random data test pattern: frame-changing and frame-fixed random data. The output type of n ly random data is decided by register 0x503E[4] (rnd_same). The random seed is set by register 0x503E[3:0] (rnd_seed). 4.3.4 transparent effect The transparent effect is enabled by register 0x503D[5] (transparent_mode).
4-5 address test pattern registers register name default value R/W description test_pattern_en 0: Disable 1: Enable Bit[6]: rolling_bar 0: Disable rolling bar 1: Enable rolling bar Bit[5]: transparent_mode 0: Disable 1: Enable Bit[4]: squ_bw_mode 0: Output square is color square 1: Output square is black-white square Bit[3:2]: bar_style When set to different value, the different type color bar will be output Bit[1:0]: test_pattern_type 00: Color bar 01: Square 10: Random data 11: Input data ISP CTRL3D
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.4 50/60Hz detection When the integration time is not an integer multiple of the period of light intensity, the image will flicker. The function of time can be determined. Contact your local OmniVision FAE for auto detection settings.
4-7 4.5 AEC and AGC algorithms n ly 4.5.1 overview The Auto Exposure Control (AEC) and Auto Gain Control (AGC) allows the image sensor to adjust the image brightness to a desired range by setting the proper exposure time and gain applied to the image. Besides automatic control, table 4-5 O exposure time and gain can be set manually from external control.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.5.2 average-based algorithm The average-based AEC controls image luminance using registers WPT (0x3A0F), BPT (0x3A10), WPT2 (0x3A1B), and BPT2 (0x3A1E). In average-based mode, the value of register WPT (0x3A0F) indicates the high threshold value for n ly image change from unstable to stable state, and the value of register BPT (0x3A10) indicates the low threshold value for image change from unstable to stable state.
4-9 average based control function registers address register name default value R/W 0x3A0F WPT 0x78 RW Bit[7:0]: WPT Stable range high limit (enter) 0x3A10 BPT 0x68 RW Bit[7:0]: BPT Stable range low limit (enter) 0x3A11 HIGH VPT 0xD0 RW Bit[7:0]: vpt_high Fast zone high limit when step ratio auto mode is disabled 0x3A1B WPT2 0x78 RW Bit[7:0]: wpt2 Stable range high limit (from stable state to unstable state) 0x3A1E BPT2 0x68 RW Bit[7:0]: bpt2 Stable range low limit (from stabl
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.5.3 average luminance (YAVG) Auto exposure time calculation is based on a frame brightness average value. By properly setting x_start, x_end, y_start, and y_end as shown in figure 4-8, a 4x4 grid average window is defined. It will automatically divide each zone into 4x4 figure 4-8 n ly zones. The average value is the weighted average of the 16 sections. table 4-7 lists the corresponding registers.
4-11 average luminance control function registers (sheet 2 of 2) address register name default value R/W 0x5685 X WINDOW 0x20 RW Bit[7:0]: Window X in manual average window mode low byte 0x5686 Y WINDOW 0x07 RW Bit[3:0]: Window Y in manual average window mode high byte 0x5687 Y WINDOW 0x98 RW Bit[7:0]: Window Y in manual average window mode low byte 0x5688 WEIGHT00 0x11 RW Bit[7:4]: Window1 weight Bit[3:0]: Window0 weight 0x5689 WEIGHT01 0x11 RW Bit[7:4]: Window3 weight Bit[3:0
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.6 AEC/AGC steps The AEC and AGC work together to obtain adequate exposure/gain based on the current environmental illumination. In n ly order to achieve the best signal-to-noise ratio (SNR), extending the exposure time is always preferred rather than raising the gain when the current illumination is getting brighter.
4-13 4.7 black level calibration (BLC) The pixel array contains several optically shielded (black) lines.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.8 strobe flash and frame exposure n ly 4.8.1 strobe flash control The strobe signal is programmable. It supports both LED and Xenon modes. The polarity of the pulse can be changed. The strobe signal is enabled (turned high/low depending on the pulse’s polarity) by requesting the signal via the SCCB interface. Flash modules are triggered by the rising edge by default or by the falling edge if the signal polarity is changed.
4-15 4.9.1 LED1 & 2 mode Two frames after the strobe request is submitted, the third frame is correctly exposed. The strobe pulse will be activated activated intermittently until the strobe end request is set (see figure 4-11). The number of skipped frames is programmable using registers {0x3A1C, 0x3A1D}. LED 1 & 2 mode - one pulse output frame in O figure 4-10 n ly only one time if the strobe end request is set correctly (see figure 4-10).
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology figure 4-11 LED 1 & 2 mode - multiple pulse output frame in is skipped n ly vertical blanking O exposure time ly data out strobe request u start tr strobe pulse request here correctly exposed frame 5647_DS_4_11 fo r the number of skipped frames is programmable 4.9.
4-17 4.10 frame exposure (FREX) mode In FREX mode, whole frame pixels start integration at the same time, rather than integrating row by row. After the n ly 4.10.1 FREX control user-defined exposure time (0x3B01, 0x3B04, 0x3B05), the shutter closes, preventing further integration and the image begins to read out. After the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for O the next FREX request.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 4.11 FREX strobe flash control table 4-10 default value register name R/W description O address FREX strobe control functions n ly See table 4-10 for FREX strobe control functions.
4-19 4.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology OTP control function registers (sheet 2 of 2) register name default value R/W description 0x3D18 OTP_DATA_24 0x00 RW OTP Buffer 18 0x3D19 OTP_DATA_25 0x00 RW OTP Buffer 19 0x3D1A OTP_DATA_26 0x00 RW OTP Buffer 1A 0x3D1B OTP_DATA_27 0x00 RW OTP Buffer 1B 0x3D1C OTP_DATA_28 0x00 RW OTP Buffer 1C 0x3D1D OTP_DATA_29 0x00 RW 0x3D1E OTP_DATA_30 0x00 RW 0x3D1F OTP_DATA_31 0x00 RW ly O address O
5-1 5 image sensor processor digital functions description Bit[7]: Bit[2]: 0x5000 ISP CTRL00 0xFF RW Bit[1]: 0x01 RW fo ISP CTRL01 0x41 n e d ISP CTRL03 Bit[0]: Bit[3]: Bit[2]: 0x0A RW fi 0x5003 Bit[1]: RW ti ISP CTRL02 a l Bit[6]: 0x5002 n Bit[1]: o C 0x5005 11.03.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address ISP general control registers (sheet 2 of 3) default value register name R/W description n ly table 5-1 Bit[5]: 0x03 RW O ISP CTRL1F ly 0x501F enable_opt 0: Not latched by VSYNC 1: Enable latched by VSYNC Bit[4]: cal_sel 0: DPC cal_start using SOF 1: DPC cal_start using VSYNC Bit[2:0]: fmt_sel 010: ISP output data 011: ISP input data bypass u 0x00 RW tr ISP CTRL25 fo r 0x5025 a l Bit[7]: ti n ISP
5-3 address ISP general control registers (sheet 3 of 3) default value register name R/W description ISP CTRL3E 0x00 RW ISP CTRL46 0x09 RW Bit[0]: fo r 0x5046 awbg_en 0: Disable 1: Enable isp_en 0: Disable 1: Enable tr Bit[3]: u ly 0x503E win_cut_en isp_test 0: Two lowest bits are 1 1: Two lowest bits are 0 Bit[4]: rnd_same 0: Frame-changing random data pattern 1: Frame-fixed random data pattern Bit[3:0]: rnd_seed Initial seed for random data pattern O Bit[6]: Bit[5]: n ly table 5-
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 5.2 lens correction (LENC) The main purpose of the LENC is to compensate for lens imperfection. According to the area where each pixel is located, n ly the module calculates a gain for the pixel, correcting each pixel with its gain calculated to compensate for the light distribution due to lens curvature.
5-5 address default value register name BR VSCALE 0x01 R/W description RW Bit[2:0]: br_vscale[10:8] Reciprocal of vertical step for BR channel. BR channel in whole image is divided into 5x5 blocks. The step is used to point to the border of the adjacent block RW Bit[7:0]: br_vscale[7:0] Reciprocal of vertical step for BR channel. BR channel in whole image is divided into 5x5 blocks.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 5.3 defect pixel cancellation (DPC) Due to processes and other reasons, pixel defects in the sensor array will occur. Thus, these bad or wounded pixels will n ly generate wrong color values. The main purpose of Defect Pixel Cancellation (DPC) function is to remove the effect caused by these bad or wounded pixels.
5-7 description Bit[6]: Bit[5]: Bit[4]: 0x5180 AWB CTRL 0x00 RW tr Bit[3]: fast_awb 0: Disable fast AWB calculation function 1: Enable fast AWB calculation function freeze_gain_en When it is enabled, the output AWB gains will be input AWB gains freeze_sum_en When it is set, the sums and averages value will be same as previous frame gain_man_en 0: Output calculated gains 1: Output manual gains set by registers start_sel 0: Select the last HREF falling edge of before gain input as calculated start si
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology AWB control registers (sheet 3 of 3) default value R/W MANUAL BLUE GAIN MSB 0x04 RW Bit[3:0]: blu_gain_man[11:8] MANUAL BLUE GAIN LSB 0x00 RW Bit[7:0]: blu_gain_man[7:0] RW Bit[7:4]: red_gain_up_limit Bit[3:0]: red_gain_dn_limit They are only the highest 4 bits of limitation.
6-1 6 image sensor output interface digital functions n ly 6.1 system control System control registers include clock, reset control, and PLL configure.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology system control registers (sheet 2 of 4) register name 0x300F SC_CMMN_PAD_ SEL1 SC_CMMN_PAD_ SEL2 R/W 0x00 RW Bit[7:0]: io_y_sel[7:0] RW Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: 0x00 description io_vsync_sel io_href_sel io_pclk_sel io_frex_sel io_strobe_sel io_sda_sel io_gpio1_sel io_gpio0_sel ly 0x3010 default value n ly address O table 6-1 u 0x02 RW tr SC_CMMN_PAD_PK 0x00 RW Bit[7
6-3 default value register name R/W description Bit[7:5]: mipi_lane_mode 0: One lane mode 1: Two lane mode Bit[4]: r_phy_pd_mipi 1: Power donw PHY HS TX Bit[3]: r_phy_pd_lprx 1: Power down PHY LP RX module Bit[2]: mipi_en 0: DVP enable 1: MIPI enable Bit[1]: mipi_susp_reg MIPI system Suspend register 1: suspend Bit[0]: lane_dis_op 0: Use mipi_release1/2 and lane_disable1/2 to disable two data lane 1: Use lane_disable1/2 to disable two data lane SC_CMMN_MIPI_ SC_CTRL 0x58 RW 0x3019 SC_CMMN_MIPI_ SC_
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology system control registers (sheet 4 of 4) default value register name 0x3034 SC_CMMN_PLL_ CTRL0 0x1A R/W description RW Bit[6:4]: pll_charge_pump Bit[3:0]: mipi_bit_mode 0000: 8 bit mode 0001: 10 bit mode Others: Reserved to future use Bit[7:4]: system_clk_div Will slow down all clocks Bit[3:0]: scale_divider_mipi MIPI PCLK/SERCLK can be slowed down when image is scaled down SC_CMMN_PLL_ CTRL1 0x11 RW 0x3036 SC_CMMN_PLL
6-5 6.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 6.3 group register write n ly The OV5647 supports group register write with up to four groups. Each group could have up to 16 registers.
6-7 6.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address timing control registers (sheet 2 of 2) default value register name R/W description n ly table 6-4 TIMING_Y_INC 0x11 RW 0x3816 TIMING_HSYNCST 0x00 RW Bit[3:0]: HSYNC start point[11:8] 0x3817 TIMING_HSYNCST 0x00 RW Bit[7:0]: HSYNC start point[7:0] 0x3818 TIMING_HSYNCW 0x00 RW 0x3819 TIMING_HSYNCW 0x00 RW 0x3820 TIMING_TC_REG20 0x40 0x3821 TIMING_TC_REG21 0x00 0x3822 TIMING_TC_REG22 0x10
6-9 strobe control registers (sheet 2 of 2) address register name default value R/W 0x3B06 STROBE_FREX_CTRL0 0x04 RW description Bit[7:6]: frex_pchg_width Bit[5:4]: frex_strobe_option Bit[3:0]: frex_strobe_width[3:0] 0x3B07 STROBE_ FREX_MODE_SEL 0x08 RW Bit[4]: Bit[3]: Bit[2]: Bit[1:0]: 0x3B08 STROBE_FREX_EXP_REQ 0x00 RW Bit[0]: frex_exp_req 0x3B09 FREX_SHUTTER_DELAY 0x00 RW Bit[2:0]: FREX end option 0x3B0A STROBE_FREX_RST_LENGTH 0x04 RW Bit[2:0]: frex_rst_length[2:0] 0x3B0B
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 6.
6-11 system control registers (sheet 2 of 2) address register name default value R/W 0x4703 DVP_HSYVSY_NEG_WIDTH 0x00 RW Bit[7:0]: VSYNC length in terms of pixel count[7:0] 0x4704 DVP VSYNC MODE 0x00 RW Bit[3:2]: r_vsyncount_sel Bit[1]: r_vsync3_mod Bit[0]: r_vsync2_mod 0x4705 DVP_EOF_VSYNC DELAY 0x00 RW Bit[7:0]: eof_vsync_delay[23:16] SOF/EOF negative edge to VSYNC positive edge delay 0x4706 DVP_EOF_VSYNC DELAY 0x00 RW Bit[7:0]: eof_vsync_delay[15:8] SOF/EOF negative edge to VSYNC
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 6.7.
6-13 table 6-8 DVP timing specifications (sheet 2 of 2) 540672 tp (2048x264) 2304 tp 13832 tp 2048 tp 34744 tp 320 tp 1728 tp O QVGA 320x240 (1) (2) (3) (4) (5) (6) (7) ly 1032192 tp (2048x504) 2304 tp 13512 tp 2048 tp 34744 tp 640 tp 1408 tp C o n fi d e n ti a l fo r tr VGA 640x480 (1) (2) (3) (4) (5) (6) (7) n ly timing u mode 11.03.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 6.8 mobile industry processor interface (MIPI) MIPI provides a single uni-directional clock lane and two bi-directional data lane solution for communication links n ly between components inside a mobile device.
6-15 default value register name R/W description RW MIPI Control 01 Bit[7]: Long packet data type manual enable 0: Use mipi_dt 1: Use dt_man_o as long packet data (see register 0x4814[5:0]) Bit[6]: Short packet data type manual enable 1: Use dt_spkt as short packet data (see register 0x4815[5:0]) Bit[5]: Short packet WORD COUNTER manual enable 0: Use frame counter or line counter 1: Select spkt_wc_reg_o (see {0x4812, 0x4813}) Bit[4]: PH bit order for ECC 0: {DI[7:0],WC[7:0],WC[15:8]} 1: {DI[0:7],WC[0:
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 6-9 default value register name R/W description n ly address MIPI transmitter registers (sheet 3 of 8) MIPI CTRL 02 0x00 RW 0x4803 MIPI CTRL 03 C o n fi d e n ti a l fo r 0x4802 tr u ly O MIPI Control 02 Bit[7]: hs_prepare_sel 0: Auto calculate T_hs_prepare, unit pclk2x 1: Use hs_prepare_min_o[7:0] Bit[6]: clk_prepare_sel 0: Auto calculate T_clk_prepare, unit pclk2x 1: Use clk_prepare_min_o[7:0]
6-17 table 6-9 default value register name R/W description RW MIPI Control 04 Bit[7]: wait_pkt_end 1: Wait HS packet end when send UL command Bit[6]: tx_lsb_first 0: lp_tx and lp_rx high bit first 1: Low power transmit low bit first Bit[5]: dir_recover_sel 0: Auto change to output only when TurnAround command 1: Auto change to output when LP11 and GPIO is output Bit[4]: mipi_reg_en 0: Disable MIPI_REG_P to access registers, LP data will write to VFIFO 1: Enable MIPI_REG_P to access registers Bit[3]:
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 6-9 default value register name R/W description RW MIPI Control 05 Bit[7]: MIPI lane1 disable 1: Disable MIPI data lane1, lane1 will be LP00 Bit[6]: MIPI lane2 disable 1: Disable MIPI data lane2, lane2 will be LP00 Bit[5]: lpx_p_sel 0: Automatically calculate t_lpx_o in pclkex domain, unit pclk2x 1: Use lp_p_min[7:0] Bit[4]: lp_rx_intr_sel 0: Send lp_rx_intr_o at the first byte 1: Send lp_rx_intr_o at the end of receiv
6-19 MIPI transmitter registers (sheet 6 of 8) R/W description MIPI MAX FRAME COUNT 0xFF RW High Byte of Max Frame Count of Frame Sync Short Packet 0x4811 MIPI MAX FRAME COUNT 0xFF RW Low Byte of Max Frame Count of Frame Sync Short Packet 0x4814 MIPI CTRL14 0x2A RW MIPI Control 14 Bit[7:6]: Virtual channel of MIPI Bit[5:0]: Data type in manual mode 0x4810 ly register name O default value address n ly table 6-9 pclk_div 0: Use rising edge of mipi_pclk_o to generate MIPI bus to PHY 1:
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology MIPI transmitter registers (sheet 7 of 8) register name default value R/W description 0x4824 LPX_P_MIN 0x00 RW High byte of the minimum value for lpx_p, unit ns Bit[1:0]: lpx_p_min[9:8] 0x4825 LPX_P_MIN 0x32 RW Low byte of the minimum value for lpx_p lpx_p_real = lpx_p_min_o + Tui*ui_lpx_p_min_o 0x4826 HS_PREPARE_MIN 0x00 RW High byte of the minimum value for hs_prepare, unit ns Bit[1:0]: hs_prepare_min[9:8] 0x4
6-21 address register name default value R/W description 0x4838 WKUP_DLY 0x02 RW Wakeup delay for MIPI 0x483A DIR_DLY 0v08 RW Change LP direction delay/2 after LP11 0x483C MIPI CTRL 33 0x4F RW 0x483D MIPI_T_TA_GO 0x10 RW t_ta_go Unit: SCLK cycles 0x483E MIPI_T_TA_SURE 0x06 RW t_ta_sure Unit: SCLK cycles 0x483F MIPI_T_TA_GET 0x14 RW t_ta_get Unit: SCLK cycles SNR_PCLK_DIV 0x00 RW u PCLK divider 0: PCLK/SCLK = 2 and pclk_div = 1 1: PCLK/SCLK = 1 and pclk_div = 1 MIPI CT
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
7-1 7 register tables The following tables provide descriptions of the device control registers contained in the OV5647.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology R/W description RW Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Bit[7:4]: Debug control Changing these registers is not recommended Bit[3:0]: io_y_sel[11:8] SC_CMMN_PAD_ OUT2 0x300E SC_CMMN_PAD_ SEL0 0x00 RW 0x300F SC_CMMN_PAD_ SEL1 0x00 RW SC_CMMN_PAD_ SEL2 0x00 tr RW n SC_CMMN_PAD_PK e 0x3011 ti a l 0x3010 fo r 0x00 d 0x3012 DEBUG MODE 0x02 RW Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bi
7-3 address system control registers (sheet 3 of 5) default value register name SC_CMMN_MIPI_ PHY 0x00 description RW Bit[7:6]: Bit[5:4]: Bit[3]: Bit[2]: lph Not used mipi_pad_enable pgm_bp_hs_en_lat Bypass the latch of hs_enable Bit[1:0]: ictl[1:0] Bias current adjustment O 0x3016 R/W n ly table 7-1 SC_CMMN_MIPI_PHY 0x10 RW fo r 0x3017 tr u ly Bit[7:6]: pgm_vcm[1:0] High speed common mode voltage Bit[5:4]: pgm_lptx[1:0] Driving strength of low speed transmitter 01 Bit[3]: ihalf Bias
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology system control registers (sheet 4 of 5) address register name default value R/W description 0x301A~ 0x3020 DEBUG MODE – – Debug Mode n ly table 7-1 0x23 RW u SC_CMMN_MISC_ CTRL fo r tr 0x3021 ly O Bit[7:6]: Not used Bit[5]: fst_stby_ctr 0: Software standby enter at v_blk 1: Software standby enter at l_blk Bit[4]: mipi_ctr_en 1: Enable MIPI remote reset and suspend control SC 0: Disable the function Bit[3]: m
7-5 system control registers (sheet 5 of 5) default value R/W SC_CMMN_PLL_ DEBUG_OPT 0x00 RW Bit[7]: pll_mult_debug_en Bit[1:0]: pll_mult1_debug 0x3039 SC_CMMN_PLL_ CTRL_R 0x00 RW Bit[7]: pll_bypass Bit[6:0]: Not used 0x303A SC_CMMN_PLLS_ CTRL0 0x00 RW Bit[7]: plls_bypass Bit[6:0]: Not used 0x303B SC_CMMN_PLLS_ CTRL1 0x19 RW Bit[7:5]: Not used Bit[4:0]: plls_multiplier 0x303C SC_CMMN_PLLS_ CTRL2 0x11 RW Bit[6:4]: plls_cp Bit[3:0]: plls_sys_div RW Bit[7:6]: Not used Bit[5:4]: plls
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-2 default value register name R/W description n ly address SCCB registers (sheet 2 of 2) 0x12 RW 0x3102 SCCB FILTER 0x00 RW O SCCB OPT tr u ly 0x3101 Bit[7:5]: en_ss_addr_inc Bit[4]: en_ss_addr_inc Bit[3]: r_sda_byp_sync 0: Two clock stage SYNC for sda_i 1: No SYNC for sda_i Bit[2]: r_scl_byp_sync 0: Two clock stage sync for scl_i 1: No sync for scl_i Bit[1]: r_msk_glitch Bit[0]: r_msk_stop Not used ct
7-7 group hold control registers register name default value R/W description 0x3200 SRM_GRUP_ADR0 0x00 RW srm_group_adr0 0x3200 GROUP ADR0 0x00 RW Group0 Start Address in SRAM, actual address is {0x3200[3:0], 0x0} 0x3201 GROUP ADR1 0x04 RW Group1 Start Address in SRAM, actual address is {0x3201[3:0], 0x0} 0x3202 GROUP ADR2 0x08 RW Group2 Start Address in SRAM, actual address is {0x3202[3:0], 0x0} 0x3203 GROUP ADR3 0x0B RW Group3 Start Address in SRAM, actual address is {0x3203[3
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-4 AEC/AGC 1 registers address register name default value R/W 0x3500 EXPOSURE 0x00 RW Bit[7:4]: Not used Bit[3:0]: Exposure[19:16] 0x3501 EXPOSURE 0x00 RW Bit[7:0]: Exposure[15:8] 0x3502 EXPOSURE 0x20 RW Bit[7:0]: Exposure[7:0] O n ly description MANUAL CTRL 0x350A AGC 0x350B AGC 0x350C VTS DIFF 0x00 RW fo r tr 0x3503 u ly Bit[7:6]: Not used Bit[5:4]: Gain latch timing delay x0: Gain
7-9 default value R/W TIMING_X_ADDR_ END 0x0A RW Bit[7:4]: Debug mode Bit[3:0]: x_addr_end[11:8] 0x3805 TIMING_X_ADDR_ END 0x33 RW Bit[7:0]: x_addr_end[7:0] 0x3806 TIMING_Y_ADDR_ END 0x07 RW Bit[7:4]: Debug mode Bit[3:0]: y_addr_end[11:8] 0x3807 TIMING_Y_ADDR_ END 0xA3 RW Bit[7:0]: y_addr_end[7:0] 0x3808 TIMING_X_OUTPUT_ SIZE 0x0A RW Bit[7:4]: Debug mode Bit[3:0]: DVP output horizontal width[11:8] 0x3809 TIMING_X_OUTPUT_ SIZE 0x20 RW Bit[7:0]: DVP output horizontal width[7:0]
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address system timing registers (sheet 3 of 3) default value register name R/W description n ly table 7-5 TIMING_Y_INC 0x11 RW 0x3816 TIMING_HSYNCST 0x00 RW Bit[7:4]: Debug mode Bit[3:0]: HSYNC start point[11:8] 0x3817 TIMING_HSYNCST 0x00 RW 0x3818 TIMING_HSYNCW 0x00 RW 0x3819 TIMING_HSYNCW 0x00 RW RW For testing only Not used For testing only r_mirror_isp r_mirror_snr r_hbin n DEBUG MODE – – Debug
7-11 default value register name R/W description Not used Less one line mode Band function Band low limit mode start_sel Night mode Not used Freeze AEC CTRL00 0x78 RW 0x3A01 MIN EXPO 0x01 RW Bit[7:0]: min expo 0x3A02 MAX EXPO 60 0x3D RW Bit[7:0]: max expo[15:8] 0x3A03 MAX EXPO 60 0x80 RW Bit[7:0]: max expo[7:0] f50_reverse 0: Hold 50, 60Hz detect input 1: Switch 50, 60Hz detect input Bit[6]: frame_insert 0: In night mode, insert frame disable 1: In night mode, insert frame enable Bit[
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-6 AEC/AGC 2 registers (sheet 2 of 3) address register name default value R/W 0x3A0C AEC CTRL0C 0xE4 RW Bit[7:4]: e1_max Decimal line high limit zone Bit[3:0]: e1_min Decimal line low limit zone 0x3A0D B60 MAX 0x08 RW Bit[7:6]: Not used Bit[5:0]: b60_max 0x3A0E B50 MAX 0x06 RW Bit[7:6]: Not used Bit[5:0]: b50_max 0x3A0F WPT 0x78 RW 0x3A10 BPT 0x68 RW Bit[7:0]: BPT Stable range low limit (enter)
7-13 AEC/AGC 2 registers (sheet 3 of 3) address register name default value R/W 0x3A1E BPT2 0x68 RW Bit[7:0]: bpt2 Stable range low limit (go out) 0x3A1F LOW VPT 0x40 RW Bit[7:0]: vpt_low Step manual mode, fast zone low limit description 0x00 RW 0x3A21 AEC CTRL21 0x70 RW Bit[7:]: Not used Bit[6:4]: Frame insert number Bit[3:0]: Not used O AEC CTRL20 default value register name R/W 0x3B01 description Strobe Control Bit[7]: Strobe request ON/OFF 0: OFF/BLC 1: ON Bit[6]: Strobe p
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology STROBE/frame exposure control registers (sheet 2 of 2) R/W 0x3B06 STROBE_FREX_CTRL0 0x04 RW Bit[7:6]: frex_pchg_width Bit[5:4]: frex_strobe_option Bit[3:0]: frex_strobe_width[3:0] Bit[4]: Bit[3]: Bit[2]: Bit[1:0]: frex_sa1 fx1_fm_en frex_inv FREX strobe 00: frex_strobe mode0 01: frex_strobe mode1 1x: Rolling strobe 0x3B07 STROBE_FREX_MODE_SEL 0x08 0x3B08 STROBE_FREX_EXP_REQ 0x00 0x3B09 FREX_SHUTTER_DELAY 0x00 RW B
7-15 default value register name 50/60 HZ DETECTION CTRL00 0x00 description Bit[7:6]: Debug control Changing these registers is not recommended Bit[5:3]: 50/60 Hz detection control Contact local OmniVision FAE for the correct settings Bit[2]: band_def Band50 default value 0: 60 Hz as default value 1: 50 Hz as default value Bit[1:0]: 50/60 Hz detection control register Contact local OmniVision FAE for the correct settings RW 50/60 HZ DETECTION CTRL01 0x00 RW 0x3C02~ 0x3C0B 50/60 HZ DETECTION CTRL0
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology register name default value R/W description 0x3D00 OTP_DATA_0 0x00 RW OTP Buffer 0 0x3D01 OTP_DATA_1 0x00 RW OTP Buffer 1 0x3D02 OTP_DATA_2 0x00 RW OTP Buffer 2 0x3D03 OTP_DATA_3 0x00 RW OTP Buffer 3 0x3D04 OTP_DATA_4 0x00 RW OTP Buffer 4 0x3D05 OTP_DATA_5 0x00 RW 0x3D06 OTP_DATA_6 0x00 RW 0x3D07 OTP_DATA_7 0x00 RW OTP Buffer 7 0x3D08 OTP_DATA_8 0x00 0x3D09 OTP_DATA_9 0x00 0x3D0A OT
7-17 address register name default value R/W description 0x3D1C OTP_DATA_28 0x00 RW OTP Buffer 1C 0x3D1D OTP_DATA_29 0x00 RW OTP Buffer 1D 0x3D1E OTP_DATA_30 0x00 RW OTP Buffer 1E 0x3D1F OTP_DATA_31 0x00 RW OTP Buffer 1F ly RW r tr 0x00 Bit[7]: OTP_wr_busy Bit[6:2]: Debug control Changing these registers is not recommended Bit[1]: OTP_program_speed 0: Fast 1: Slow Bit[0]: OTP_program_enable Changing from 0 to 1 initiates OTP programming u OTP_PROGRAM_ CTRL 0x3D20 n ly OTP
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology n ly default value register name R/W description BLC Control (0: disable ISP; 1: enable ISP) Bit[7]: blc_median_filter_enable Bit[6:4]: Not used Bit[3]: adc_11bit_mode Bit[2]: apply2blackline Bit[1]: blackline_averageframe Bit[0]: BLC enable BLC CTRL00 0x89 RW 0x4001 BLC CTRL01 0x00 RW Bit[7:6]: Not used Bit[5:0]: start_line u 0x4000 O address BLC registers (sheet 1 of 3) ly table 7-10 BLC CTRL02 0x45 RW r
7-19 default value register name R/W description Bit[7:5]: Not used Bit[4:3]: win_sel 00: Full image 01: Windows do not contain the first 16 pixels and the last 16 pixels 10: Windows do not contain the first 1/16 image and the last 1/16 image 11: Windows do not contain the first 1/8 image and the last 1/8 image Bit[2:0]: Bypass_mode 000: Bypass data_i after limit bits 001: Bypass data_i[11:0] 011: Bypass data_i[12:1] 100: Bypass debug data bbrr 101: Bypass debug data gggg 1xx: Not used BLC CTRL07 0x00
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-10 BLC registers (sheet 3 of 3) address register name default value R/W 0x402E BLACK_LEVEL01 – R Bit[7:0]: blacklevel01[15:8] 0x402F BLACK_LEVEL01 – R Bit[7:0]: blacklevel01[7:0] 0x4030 BLACK_LEVEL10 – R Bit[7:0]: blacklevel10[15:8] 0x4031 BLACK_LEVEL10 – R Bit[7:0]: blacklevel10[7:0] 0x4032 BLACK_LEVEL11 – R Bit[7:0]: blacklevel11[15:8] 0x4033 BLACK_LEVEL11 – R 0x4050 BLC MAX 0xFF RW
7-21 default value register name R/W description FRAME CTRL0 0x00 RW 0x4201 FRAME ON NUMBER 0x00 RW Bit[7:4]: Not used Bit[3:0]: Frame ON number 0x4202 FRAME OFF NUMBER 0x00 RW Bit[7:4]: Not used Bit[3:0]: Frame OFF number RW Bit[7:6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: u 0x00 tr FRAME CTRL1 Not used data_mask_dis valid_mask_dis href_mask_dis eof_mask_dis sof_mask_dis all_mask_dis 0x4701 VSYNC WIDTH 0x4702 0x4703 l ti MODE SELECT R/W 0x04 RW description Bit[7:4
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology DVP registers (sheet 2 of 2) register name 0x4707 EOF VSYNC_DELAY_0 POLARITY CTRL R/W 0x00 RW Bit[7:0]: eof_vsync_delay[7:0] SOF/EOF negative edge to VSYNC positive edge delay RW Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: 0x01 description Clock DDR mode enable Not used VSYNC gate clock enable HREF gate clock enable No frst for FIFO HREF polarity reverse option VSYNC polarity reverse option PCLK pol
7-23 default value register name R/W description RW MIPI Control 00 Bit[7]: mipi_hs_only 0: MIPI can support CD and ESCAPE mode 1: MIPI always in high speed mode Bit[6]: ck_mark1_en 0: Not used 1: Enable clock lane mark1 when resume Bit[5]: Clock lane gate enable 0: Clock lane is free running 1: Gate clock lane when no packet to transmit Bit[4]: Line sync enable 0: Do not send line short packet for each line 1: Send line short packet for each line Bit[3]: Lane select 0: Use lane1 as default data lane
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-13 default value register name R/W description n ly address MIPI top registers (sheet 2 of 11) tr u ly O MIPI Control 01 Bit[7]: Long packet data type manual enable 0: Use mipi_dt 1: Use dt_man_o as long packet data (see register 0x4814[5:0]) Bit[6]: Short packet data type manual enable 1: Use dt_spkt as short packet data (see register 0x4815[5:0]) Bit[5]: Short packet WORD COUNTER manual enable 0: Use frame co
7-25 table 7-13 default value register name R/W description RW MIPI Control 02 Bit[7]: hs_prepare_sel 0: Auto calculate T_hs_prepare, unit pclk2x 1: Use hs_prepare_min_o[7:0] Bit[6]: clk_prepare_sel 0: Auto calculate T_clk_prepare, unit pclk2x 1: Use clk_prepare_min_o[7:0] Bit[5]: clk_post_sel 0: Auto calculate T_clk_post, unit pclk2x 1: Use clk_post_min_o[7:0] Bit[4]: clk_trail_sel 0: Auto calculate T_clk_trail, unit pclk2x 1: Use clk_trail_min_o[7:0] Bit[3]: hs_exit_sel 0: Auto calculate T_hs_exit,
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-13 default value register name R/W description RW MIPI Control 03 Bit[7:6]: lp_glitch_nu 0: Use 2d of lp_in 1: Mask one SCLK cycle glitch of lp_in Bit[5:4]: cd_glitch_nu 0: Use 2d of lp_cd_in 1: Mask one SCLK cycle glitch of lp_cd_in Bit[3]: Enable CD plus of data lane1 0: Disable 1: Enable Bit[2]: Enable CD plus of data lane2 0: Disable 1: Enable Bit[1]: Enable CD of data_lane1 from PHY 0: Disable 1: Enable Bit[0]:
7-27 table 7-13 default value register name R/W description RW MIPI Control 04 Bit[7]: wait_pkt_end 0: Not used 1: Wait HS packet end when send UL command Bit[6]: tx_lsb_first 0: lp_tx and lp_rx high bit first 1: Low power transmit low bit first Bit[5]: dir_recover_sel 0: Auto change to output only when TurnAround command 1: Auto change to output when LP11 and GPIO is output Bit[4]: mipi_reg_en 0: Disable MIPI_REG_P to access registers, LP data will write to VFIFO 1: Enable MIPI_REG_P to access regis
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-13 default value register name R/W description n ly address MIPI top registers (sheet 6 of 11) MIPI CTRL 05 0x10 RW C o n fi d e n ti a l fo r 0x4805 tr u ly O MIPI Control 05 Bit[7]: MIPI lane1 disable 0: Not used 1: Disable MIPI data lane1, lane1 will be LP00 Bit[6]: MIPI lane2 disable 0: Not used 1: Disable MIPI data lane2, lane2 will be LP00 Bit[5]: lpx_p_sel 0: Automatically calculate t_lpx
7-29 Bit[7]: Bit[6]: Bit[5]: Bit[4]: 0x4806 MIPI REG RW CTRL 0x28 Bit[3]: Bit[2]: RW Test mode mipi_test mipi_lp_op 0: Use new option to reduce mipi_lptx_p 1: Not used two_lane_man_en 0: Not used 1: Use two_lane_man to manually control two_lane_mode two_lane_man rst_rtn_en 0: Not used 1: Change to input to allow host RW register after reset frame_end_en 0: Not used 1: After frame end packet, change to input to allow host RW register line_end_en 0: Not used 1: After line end packet, change to input t
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-13 MIPI top registers (sheet 8 of 11) register name default value R/W description 0x4819 HS_ZERO_MIN 0x96 RW Low byte of the minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + Tui*ui_hs_zero_min_o 0x481A HS_TRAIL_MIN 0x00 RW High byte of the minimum value for hs_trail, unit ns 0x481B HS_TRAIL_MIN 0x3C RW Low byte of the minimum value for hs_trail, hs_trail_real = hs_trail_min_o + Tui*ui_hs
7-31 table 7-13 MIPI top registers (sheet 9 of 11) register name default value R/W description 0x4827 HS_PREPARE_MIN 0x32 RW Low byte of the minimum value for hs_prepare hs_prepare_real = hs_prepare_min_o + Tui*ui_hs_prepare_min_o 0x4828 HS_EXIT_MIN 0x00 RW High byte of the minimum value for hs_exit, unit ns Bit[7:2]: Not used Bit[1:0]: hs_exit_min[9:8] 0x4829 HS_EXIT_MIN 0x64 RW Low byte of the minimum value for hs_exit hs_exit_real = hs_exit_min_o + Tui*ui_hs_exit_min_o 0x482A UI_HS_
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology default value register name R/W description Bit[7]: Bit[6]: 0x33 RW Bit[5]: Bit[4]: Bit[3]: tr fo r Bit[2]: MIPI CTRL 33 0x483D MIPI_T_TA_GO 0x483E MIPI_T_TA_SURE a ti n MIPI_T_TA_GET RW d SNR_PCLK_DIV t_ta_go Unit: SCLK cycles 0x06 RW t_ta_sure Unit: SCLK cycles 0x14 RW t_ta_get Unit: SCLK cycles 0x00 RW n o C Bit[7:4]: t_lpx, unit: sclk cycles Bit[3:0]: t_clk_pre, unit: sclk cycles RW fi 0x484
7-33 address MIPI top registers (sheet 11 of 11) default value register name R/W description n ly table 7-13 MIPI_ST – R 0x4866 T_GLB_TIM_H – R Bit[7]: VHREF ahead of flag, must delay vhref Bit[6:0]: vhref_delay_h 0x4867 T_GLB_TIM_L – R fo l vhref_delay_l a ti default value register name R/W description 0x00 RW Bit[7:3]: Bit[2]: Bit[1]: Bit[0]: n address ISPFC registers e table 7-14 r tr u ly O 0x4865 Bit[7:6]: Not used Bit[5]: lp_rx_sel_i 0: Not used 1: MIPI_LP_RX
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address ISP TOP control registers (sheet 1 of 6) default value register name R/W description n ly table 7-15 ISP CTRL00 0xFF RW 0x01 RW tr ISP CTRL01 ISP CTRL02 0x41 RW l 0x5002 fo r 0x5001 u ly 0x5000 lenc_en 0: Disable 1: Enable Bit[6:3]: Not used Bit[2]: bc_en 0: Disable 1: Enable Bit[1]: wc_en 0: Disable 1: Enable Bit[0]: Not used O Bit[7]: a ti 0x0A RW RW Bit[7:4]: Not used Bit[3]: size_man_en 0
7-35 address ISP TOP control registers (sheet 2 of 6) default value register name R/W description sof_man 0: SOF from BLC module 1: SOF from pre_isp module Bit[6]: awb_bias_man_en 0: AWB bias manual disable 1: AWB bias manual enable Bit[5]: awb_bias_on 0: Disable AWB bias 1: Enable AWB bias Bit[4:3]: Not used Bit[2]: lenc_bias_on 0: Disable LENC bias 1: Enable LENC bias Bit[1]: Disable LENC bias s2p_sw_en_o Bit[0]: Disable LENC bias avg_en 0: Disable 1: Enable ISP CTRL05 0x31 RW r tr u 0x5005 l
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address register name default value R/W 0x500C WIN X OFFSET MAN 0x00 RW Bit[7:4]: Not used Bit[3:0]: win_x_offset_man[11:8] 0x500D WIN X OFFSET MAN 0x00 RW Bit[7:0]: win_x_offset_man[7:0] 0x500E WIN Y OFFSET MAN 0x00 RW Bit[7:3]: Not used Bit[2:0]: win_y_offset_man[10:8] 0x500F WIN Y OFFSET MAN 0x00 RW Bit[7:0]: win_y_offset_man[7:0] 0x5010 WIN X OUT MAN 0x00 RW 0x5011 WIN X OUT MAN 0x00 RW 0x5012
7-37 ISP CTRL1F 0x03 R/W description RW Bit[7:6]: Not used Bit[5]: enable_opt 1: Enable latched by VSYNC 0: Not latched by VSYNC Bit[4]: cal_sel 0: DPC cal_start using SOF 1: DPC cal_start using VSYNC Bit[3]: Not used Bit[2:0]: fmt_sel 0: ISP output data 1: ISP input data bypass Bit[7:4]: Not used Bit[1:0]: avg_sel 00: Inputs of AVG module are from LENC output 01: Inputs of AVG module are from AWB gain output 10: Inputs of AVG module are from DPC output 11: Inputs of AVG module are from binning output
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address ISP TOP control registers (sheet 5 of 6) default value register name R/W description n ly table 7-15 ISP CTRL3E 0x00 RW u ly 0x503E Not used win_cut_en isp_test 0: Two lowest bits are 1 1: Two lowest bits are 0 Bit[4]: Two lowest bits are rnd_same 0: Frame-changing random data pattern 1: Frame-fixed random data pattern Bit[3:0]: rnd_seed Initial seed for random data pattern O Bit[7]: Bit[6]: Bit[5]: tr ISP
7-39 default value register name R/W description ISP CTRL57 0x00 RW 0x5058 ISP CTRL58 0xAA RW Bit[7:4]: sram_rm_dpc1 Bit[3:0]: sram_rm_dpc2 0x5059 ISP CTRL59 0xAA RW Bit[7:4]: sram_rm_dpc3 Bit[3:0]: sram_rm_dpc4 u default value register name R/W description r address AWB registers (sheet 1 of 3) tr table 7-16 sram_test_dpc1 sram_test_dpc2 sram_test_dpc3 sram_test_dpc4 Not used ly 0x5057 Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3:0]: n ly address ISP TOP control registers (sheet
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address AWB registers (sheet 2 of 3) default value register name R/W AWB DELTA 0x20 RW 0x5182 STABLE RANGE 0x04 RW Bit[7:0]: stable_range 0x5183 STABLE RANGEW 0x08 RW Bit[7:0]: stable_rangew Wide stable range 0x5184 HSIZE_MAN 0x01 RW 0x5185 HSIZE_MAN 0xE0 0x5186 MANUAL RED GAIN MSB 0x04 RW Bit[7:4]: Not used Bit[3:0]: red_gain_man[11:8] 0x5187 MANUAL RED GAIN LSB 0x00 RW Bit[7:0]: red_gain_man[7:0]
7-41 address AWB registers (sheet 3 of 3) default value register name R/W description BLUE GAIN LIMIT 0xF0 RW 0x518F FRAME CNT 0x00 RW Bit[7:4]: Not used Bit[3:0]: awb_frame_cnt 0x51DF BASE MAN 0x10 RW Bit[7:0]: base_man u tr register name default value R/W 0x5680 X START 0x00 RW 0x5681 X START 0x00 0x5682 Y START 0x5683 Y START 0x5684 X WINDOW description Bit[7:5]: Not used Bit[4:0]: x_start[11:8] Horizontal start position for average window high byte a l address r
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-17 average registers (sheet 2 of 2) address register name default value R/W 0x5689 WEIGHT01 0x11 RW Bit[7:4]: window3_weight Bit[3:0]: window2_weight 0x568A WEIGHT02 0x11 RW Bit[7:4]: window5_weight Bit[3:0]: window4_weight 0x568B WEIGHT03 0x11 RW Bit[7:4]: window7_weight Bit[3:0]: window6_weight 0x568C WEIGHT04 0x11 RW Bit[7:4]: window9_weight Bit[3:0]: window8_weight 0x568D WEIGHT05 0x11 RW
7-43 LENC registers (sheet 1 of 4) address register name default value R/W 0x5800 GMTRX00 0x10 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_00 0x5801 GMTRX01 0x10 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_01 0x5802 GMTRX02 0x10 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_02 0x5803 GMTRX03 0x10 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_03 0x5804 GMTRX04 0x10 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_04 0x5805 GMTRX05 0x10 RW Bit[7:6]: Not used Bit[5:0]: green_matr
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-19 LENC registers (sheet 2 of 4) address register name default value R/W 0x5812 GMTRX30 0x10 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_12 0x5813 GMTRX31 0x08 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_13 0x5814 GMTRX32 0x00 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_14 0x5815 GMTRX33 0x00 RW Bit[7:6]: Not used Bit[5:0]: green_matrix_15 0x5816 GMTRX34 0x08 RW 0x5817 GMTRX35 0x10 0x581
7-45 LENC registers (sheet 3 of 4) address register name default value R/W 0x5825 BRMATRX01 0xAA RW Bit[7:4]: blue_matrix_01 Bit[3:0]: red_matrix_01 0x5826 BRMATRX02 0xAA RW Bit[7:4]: blue_matrix_02 Bit[3:0]: red_matrix_02 0x5827 BRMATRX03 0xAA RW Bit[7:4]: blue_matrix_03 Bit[3:0]: red_matrix_03 0x5828 BRMATRX04 0xAA RW Bit[7:4]: blue_matrix_04 Bit[3:0]: red_matrix_04 0x5829 BRMATRX05 0xAA RW Bit[7:4]: blue_matrix_05 Bit[3:0]: red_matrix_05 0x582A BRMATRX06 0x99 RW Bit[7:4
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology table 7-19 LENC registers (sheet 4 of 4) address register name default value R/W 0x5838 BRMATRX40 0xAA RW Bit[7:4]: blue_matrix_40 Bit[3:0]: red_matrix_40 0x5839 BRMATRX41 0xAA RW Bit[7:4]: blue_matrix_41 Bit[3:0]: red_matrix_41 0x583A BRMATRX42 0xAA RW Bit[7:4]: blue_matrix_42 Bit[3:0]: red_matrix_42 0x583B BRMATRX43 0xAA RW Bit[7:4]: blue_matrix_43 Bit[3:0]: red_matrix_43 0x583C BRMATRX44 0xAA RW ly
7-47 cluster DPC registers (sheet 2 of 2) address register name default value R/W 0x5907 OTP CTRL07 0x38 RW Bit[7]: Not used Bit[6:4]: remain_bit Bit[3:0]: Threshold 0x5908 OTP MAN X EVEN INC 0x01 RW Bit[7:4]: Not used Bit[3:0]: otp_man_x_even_inc 0x5909 OTP MAN X ODD INC 0x01 RW Bit[7:4]: Not used Bit[3:0]: otp_man_x_odd_inc 0x590A OTP MAN Y EVEN INC 0x01 RW Bit[7:4]: Not used Bit[3:0]: otp_man_y_even_inc 0x590B OTP MAN Y ODD INC 0x01 RW Bit[7:4]: Not used Bit[3:0]: otp_man_y_
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology address AEC/AGC 3 registers default value register name R/W description Not used dig_comp_bypass man_opt man_en DIGC CTRL0 0x00 RW 0x5A02 DIG COMP MAN 0x02 RW Bit[7:2]: Not used Bit[1:0]: dig_comp_man[9:8] 0x5A03 DIG COMP MAN 0x00 RW Bit[7:0]: dig_comp_man[7:0] 0x5A20 SNR GAIN MAN 0x00 RW 0x5:A21 SNR GAIN MAN 0x00 RW 0x5A22 DIG GAIN MAN 0x00 0x5A23 DIG GAIN MAN 0x00 0x5A24 GAINC CTRL0 0x5A25 ly
8-1 8 operating specifications table 8-1 absolute maximum ratings ambient storage temperature -40°C to +125°C VDD-D 3V VDD-IO 4.5V human body model 2000V machine model electro-static discharge (ESD) 200V -0.3V to VDD-IO + 1V r all input/output voltages (with respect to ground) ±200 mA fo I/O current on any input or output pin a. ly 4.5V u supply voltage (with respect to ground) VDD-A O absolute maximum ratinga tr parameter n ly 8.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 8.3 DC characteristics table 8-3 symbol parameter min typ VDD-A supply voltage (analog) 2.6 2.8 VDD-DO supply voltage (digital I/O) 1.7 a supply voltage (digital core) 1.425 VDD-E supply voltage (MIPI) 1.
8-3 table 8-4 symbol AC characteristics (TA = 25°C, VDD-A = 2.8V) parameter min typ max unit analog bandwidth 48 DLE DC differential linearity error 0.
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
9-1 9 mechanical specifications figure 9-1 die specifications 22 ly 100 μm 100 μm u 154 μm 77 μm O 374 (2760, 2350) 20 μm 1 284 205 254 277 234 207 176 160 208 168 209 207 234 234 386 247 234 166 151 267 (-2760, 2350) 277 352 5520 μm n ly 9.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology x coordinate y coordinate x pitch 9 GPIO0 -437 2280 234 10 STROBE -203 2280 234 11 FREX 31 2280 234 12 DOVDD 238 2280 13 VREF2 414 14 VREF1 15 0 77x100 0 77x100 207 0 77x100 2280 176 0 77x100 574 2280 160 0 77x100 PWDN 782 2280 208 0 77x100 16 DVDD 950 2280 168 0 77x100 17 RESETB 1159 2280 209 0 77x100 18 AVDD 1366 2280 207 0 154x100 19 AGND 1643 2280 277
9-3 pad location coordinates (sheet 3 of 3) pad name x coordinate y coordinate x pitch y pitch pad size 39 D6/MCP -490 -2280 -150 0 77x100 40 EGND -656 -2280 -166 0 77x100 41 D5/MDN1 -806 -2280 -150 0 77x100 42 D4/MDP1 -956 -2280 -150 0 77x100 43 EGND -1122 -2280 -166 0 77x100 44 PVDD -1298 -2280 -176 0 77x100 45 XCLK -1466 -2280 -168 0 46 DOVDD -1667 -2280 -201 47 DVDD -1875 -2280 -208 48 DOGND -2051 -2280 49 AVDD -2279 -2280 50 AGND
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
10-1 10 optical specifications figure 10-1 n ly 10.1 sensor array center sensor array center 1 O 3670 μm 22 u ly first pixel readout (-2155 μm, 1195 μm) tr package center (0 μm, 0 μm) array center (-320 μm, -175 μm) fo r 2740 μm a l sensor array OV5647 23 ti 50 n top view e note 1 this drawing is not to scale and is for reference only.
OV5647 color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology 10.2 lens chief ray angle (CRA) figure 10-2 n ly chief ray angle (CRA) 30.0 O 25.0 ly u 15.0 tr 10.0 0.80 0.0 0.114 2.0 0.10 0.227 4.1 0.15 0.341 6.1 0.20 0.454 8.1 0.25 0.568 10.1 0.30 0.681 12.0 0.35 0.795 13.8 0.40 0.908 15.6 0.45 1.022 17.3 0.50 1.135 18.9 d fi n 0.60 0.000 0.05 o 0.40 CRA (degrees) 0.
10-3 table 10-1 CRA versus image height plot (sheet 2 of 2) image height (mm) CRA (degrees) 0.55 1.249 20.4 0.60 1.362 21.6 0.65 1.476 22.6 0.70 1.589 23.4 0.75 1.703 23.9 0.80 1.816 24.1 0.85 1.930 24.1 0.90 2.043 23.9 0.95 2.157 23.7 1.00 2.270 23.6 C o n fi d e n ti a l fo r tr u ly O n ly field (%) 11.03.
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
rev-1 revision history 11.03.2009 initial release C o n fi d e n ti a l fo r tr u ly O • n ly version 1.0 11.03.
OV5647 C o n fi d e n ti a l fo r tr u ly O n ly color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.
OmniVision Technologies, Inc. UNITED STATES 4275 Burton Drive Santa Clara, CA 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.
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