Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
6-17
0x4804 MIPI CTRL 04 0x8D RW
MIPI Control 04
Bit[7]: wait_pkt_end
1: Wait HS packet end when send UL
command
Bit[6]: tx_lsb_first
0: lp_tx and lp_rx high bit first
1: Low power transmit low bit first
Bit[5]: dir_recover_sel
0: Auto change to output only when
TurnAround command
1: Auto change to output when LP11
and GPIO is output
Bit[4]: mipi_reg_en
0: Disable MIPI_REG_P to access
registers, LP data will write to VFIFO
1: Enable MIPI_REG_P to access
registers
Bit[3]: Address read/write register will auto add 1
0: Disable
1: Enable
Bit[2]: LP TX lane select
0: Select lane1 to transmit LP data
1: Select lane2 to transmit LP data
Bit[1]: wr_first_byte
1: lp_rx will write first byte (command
byte) to RAM
Bit[0]: rd_ta_en
1: Send TurnAround command after
sending register read data
table 6-9 MIPI transmitter registers (sheet 4 of 8)
address register name
default
value R/W description