Diagonal 4.60 mm (Type 1/4.0) 8 Mega-Pixel CMOS Image Sensor with Square Pixel for Color Cameras IMX219PQH5-C Description The IMX219PQH5-C is a diagonal 4.60 mm (Type 1/4.0) CMOS active pixel type image sensor with a square pixel array and 8.08M effective pixels. This chip operates with three power supplies, analogue 2.8 V, digital 1.2 V, and IF 1.8 V, and has low power consumption.
IMX219PQH5-C Device Structure ◆ CMOS image sensor ◆ Image size : Diagonal 4.60 mm (Type 1/4.0) ◆ Total number of pixels ◆ Number of effective pixels ◆ Number of active pixels ◆ Chip size ◆ Unit cell size ◆ Substrate material : 3296 (H) × 2512 (V) approx. 8.28 M pixels : 3296 (H) × 2480 (V) approx. 8.17 M pixels : 3280 (H) × 2464 (V) approx. 8.08 M pixels : 5.095 mm (H) × 4.930 mm (V) (w/ Scribe) : 1.12 µm (H) × 1.
IMX219PQH5-C USE RESTRICTION NOTICE This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice.
IMX219PQH5-C Contents Description...................................................................................................................................................... 1 Features ......................................................................................................................................................... 1 Device Structure .............................................................................................................................................
IMX219PQH5-C 4-1-5 CSI-2 Frame Format ................................................................................................................... 49 4-1-6 CSI-2 Embedded Data Line......................................................................................................... 50 5-1 Pixel Array Physical Image ................................................................................................................ 52 5-2 Pixel Binning Mode .............................................
IMX219PQH5-C 9-2 Clock Setting Example ...................................................................................................................... 82 9-3 Temperature Sensor .......................................................................................................................... 83 10. Electrical Characteristics....................................................................................................................... 84 10-1 Absolute Maximum Ratings ................
IMX219PQH5-C Table of Figures Fig. 1 Block Diagram .............................................................................................................................. 10 Fig. 2 Pin Equivalent Circuit .................................................................................................................... 13 Fig. 3 Chip Center and Optical Center..................................................................................................... 14 Fig.
IMX219PQH5-C Fig. 39 Start streaming sequence with 2-wire serial communication (external reset) ................................ 78 Fig. 40 Power-off Sequence in 2-wire Serial Communication................................................................... 79 Fig. 41 Software Standby Operation Pattern 1 ........................................................................................ 80 Fig. 42 Software Standby Operation Pattern 2 .....................................................................
IMX219PQH5-C Table 26 Description of Test Pattern Registers ........................................................................................ 63 Table 27 Description of Test Patterns ...................................................................................................... 64 Table 28 Black Level Adjust Setting Register ........................................................................................... 67 Table 29 Pixel Re-alignment H Direction Setting Registers .................
IMX219PQH5-C 1. Block Diagram and Pin Configuration 1-1 Block Diagram Fig. 1 Block Diagram 1-2 Pin Description Table 1 Pin Description Pin No. Symbol I/O A/D Description Remarks 1 VDDLSC1 Power D 1.2 V Power 2 VSSLSC1 GND D 1.2 V GND 3 VDDHCM1 Power A 2.8 V Power 4 VSSHCM1 GND A 2.8 V GND 5 VSSLCN1 GND D 1.2 V GND 6 VDDLCN1 Power D 1.2 V Power 7 VSSLDM1 8 VSSLSC2 GND D 1.2 V GND 9 VDDHFIL1 Power A 2.8 V Power 10 VDDLCN2 Power D 1.
IMX219PQH5-C Pin No. Symbol I/O A/D Description Remarks 19 VDDHSN1 Power A 2.8 V Power 20 VSSLSC4 GND D 1.
IMX219PQH5-C Pin No. Symbol I/O A/D Description Remarks 58 VSSHPL GND D 2.8 V GND 59 VDDHPL Power D 2.8 V Power 60 TVCDSIN I A Analog Input NC, For test 61 TVMON O A Analog Output NC, For test 62 VSSHAN GND A 2.8 V GND 63 VDDHAN Power A 2.8 V Power 64 VDDHSN2 Power A 2.8 V Power 65 VSSHSN2 GND A 2.
IMX219PQH5-C 1-3 Pin Equivalent Circuit Symbol Equivalent circuit Symbol VSSH VCP Equivalent circuit Analog Output Analog Output VBO VSSH VDIG VDIG Digital Input Digital Input XCLR INCK VSSL VSSL VDIG VDIG Digital I/O VDIG Digital I/O SDA SCL VSSL VDIG GPO VSSL Schmitt Buffer VSSL VDIG VDIG VDIG VDIG Digital Output FSTROBE POREN VDIG Analog Input VSSL VSSL VDDH: 2.8 V power supply, VDIG: 1.8 V power supply, VDDL: 1.2 V power supply VSSH: 2.8 V GND, VSSL: 1.2 V GND Fig.
IMX219PQH5-C 1-4 Chip Center, Optical Center and Pin Assignment (Unit: µm) Fig.
IMX219PQH5-C 1-5 Pin Coordinates Table 2 Pin Coordinates Pin No. Symbol X (pad center) Y (pad center) Pin No. Symbol X (pad center) Y (pad center) 1 VDDLSC1 2247.50 2355.00 35 VDDLSC6 -2447.50 -2165.00 2 VSSLSC1 1767.50 2355.00 36 VSSLSC6 -2247.50 -2365.00 3 VDDHCM1 1647.50 2355.00 37 VSSLDM2 -2127.50 -2365.00 4 VSSHCM1 1407.50 2355.00 38 VDDLSC7 -807.50 -2365.00 5 VSSLCN1 1167.50 2355.00 39 VSSLSC7 -567.50 -2365.00 6 VDDLCN1 687.50 2355.
IMX219PQH5-C 2. Pixel Signal Output Specifications IMX219PQH5-C has CSI-2 interface and the options are 4 lanes or 2lanes. 2-1 CSI-2 Signalling Mode 2-1-1 MIPI Transmitter Output pin of CSI-2 are shown below MIPI Block DMO1P/N Lane 1 DMO2P/N Lane 2 DCKP/N Clock Lane DMO3P/N Lane 3 DMO4P/N Lane 4 Fig. 4 Relationship between Output pin name and MIPI output Lane Data and clock signals are transmitted using CSI-2 interface (high speed serial interface).
IMX219PQH5-C 3. Control Registers The IMX219PQH5-C can use the 2-wire serial communication method for sensor control. These specifications are described for sensor control using the 2-wire serial communication as follows. 3-1 2-wire Serial Communication Operation Specifications The 2-wire serial communication method conforms to the Camera Control Instance (CCI). CCI is an I2C fast-mode plus ( INCK[fSCK] = 11.4 to 27 MHz) compatible interface, and the data transfer protocol is I2C standard.
IMX219PQH5-C Bus free state SDA MSB SDA S A7 LSB A6 A5 A4 A3 A2 A1 R/W ACK SCL SCL Data sampling The Data changeds while the clock is Low. Start Condition Fig. 7 Start Condition MSB SDA ACK/NACK SDA S A7 A6 A5 A4 A3 SCL SCL Start Condition The Stop condition is not generated. Fig. 8 Repeated Start Condition The Stop condition is defined by SDA changing from Low to High while SCL is High.
IMX219PQH5-C SDA SDA SCL SCL SDA SDA SCL SCL D1 D0 R/W ACK D1 D0 R/W NACK Fig. 11 Acknowledge and Negative Acknowledge The registers have a 16-bit address space, and are assigned as follows.
IMX219PQH5-C 3-1-2-1 CCI single read from random location The sensor has an index function that indicates which address it is focusing on. In reading the data at an optional single address, the Master must set the index value to the address to be read. For this purpose it performs dummy write operation up to the register address. The upper level of the figure below shows the sensor internal index value, and the lower level of the figure shows the SDA I/O data flow.
IMX219PQH5-C 3-1-2-3 CCI sequential read starting from random location In reading data sequentially, which is starting from an optional address, the Master must set the index value to the start of the addresses to be read. For this purpose, dummy write operation includes the register address setting. The Master sets the sensor index value to M by designating the sensor slave address with a read request, then designating the address (M). Then, the Master generates the Repeated Start condition.
IMX219PQH5-C 3-1-2-5 CCI single write to random location The Master sets the sensor index value to M by designating the sensor slave address with a write request, and designating the address (M). After that the Master can write the value in the designated register by transmitting the data to be written. After writing the necessary data, the Master generates the Stop condition to end the communication.
IMX219PQH5-C 3-1-3 2-wire serial communication block characteristics The block operation specifications for 2-wire serial communication are show below. Repeated Start Condition Start Condition Stop Condition tBUF SDA tR tF SCL tSUDAT tHIGH tLOW tSUSTA tHDDAT tHDSTA tSUSTO tHDSTA Fig. 18 2-wire Serial Communication Specifications Table 7 2-wire Serial Communication Operation Specifications Item Symbol Conditions Min. Max. Unit Low level input voltage VIL -0.5 0.
IMX219PQH5-C Table 9 2-wire Serial Communication AC Timing (Fast mode) Item Symbol Min. Max. Unit SCL clock frequency ( INCK[fSCK] = 6 to 27 MHz) fSCL 0 400 kHz Rise time (SDA and SCL) tR ― 300 ns Fall time (SDA and SCL) tF ― 300 ns Hold time (start condition) tHDSTA 0.6 ― µs Setup time (rep.-start condition) tSUSTA 0.6 ― µs Setup time (stop condition) tSUSTO 0.6 ― µs Data setup time tSUDAT 100 ― ns Data hold time tHDDAT 0 0.
IMX219PQH5-C 3-1-5 Register Synchronization (Frame Bank) Sequence for control of frame bank is explained in this section: 1. 2. All registers on frame bank are latched by vertical synchronization (V-sync) signal. Any change for registers on frame bank are reflected to functions in next frame (or following next frame) if the corresponding registers are updated. Figures for sequences of frame bank are shown in following statements.
IMX219PQH5-C 3-2 2-wire Serial Communication Register Map (Configuration register, Parameter limit register) 3-2-1 Configuration Registers – [0x0000-0x0FFF] 3-2-1-1 Status Registers – [0x0000-0x001B] (Read Only Dynamic Registers) Index Byte Register Name RW 0000 [7:0] MODEL_ID[15:8] RO 0001 [7:0] MODEL_ID[7:0] RO 0004 [7:0] Lot_ID[23:16] Comment model id ReTime Default (HEX) Embd DL 02 19 RO-D Lot_ID of the sensor Copied from NVM XX ○ XX ○ XX ○ 0005 [7:0] Lot_ID[15:8] RO-D 00
IMX219PQH5-C 3-2-1-2 Frame Format Description – [0x0040-0x0047] Index Byte Register Name 0x0040 [7:0] FRM_FMT_TYPE[7:0] RO 0x0041 [7:0] FRM_FMT_SUBTYPE[7:0] RO 0x0042 [7:0] FRM_FMT_DESC0[15:8] RO-D 0x0043 [7:0] FRM_FMT_DESC0[7:0] 0x0044 [7:0] FRM_FMT_DESC1[15:8] [7:0] FRM_FMT_DESC1[7:0] 0x0046 [7:0] FRM_FMT_DESC2[15:8] [7:0] 01 ○ frame_format_model_subtype 12 ○ 5C ○ D0 ○ 10 ○ 02 ○ 59 ○ A0 ○ Default Embd DL frame_format_descriptor_1 RO-D 0x0047 frame_format_mod
IMX219PQH5-C 3-2-1-4 Data Format Description – [0x00C0-0x00D1] Index Byte 0x00C0 [7:0] 0x00C1 0x00C2 Register Name Embd DL data_format_model_type 01 ○ RO data_format_model_subtype 01 ○ 0A ○ RO data_format_descriptor_0 08 ○ 0A ○ 0A ○ Default (HEX) Embd DL Comment DT_FMT_TYPE[7:0] RO [7:0] DT_FMT_SUBTYPE[7:0] [7:0] DT_FMT_DESC0[15:8] 0x00C3 [7:0] DT_FMT_DESC0[7:0] 0x00C4 [7:0] DT_FMT_DESC1[15:8] RO 0x00C5 [7:0] ReTime Default (HEX) RW data_format_descriptor_1 DT_FM
IMX219PQH5-C 3-2-2-2 Output Set-up Registers – [0x0110-0x0147] Default (HEX) Embd DL CSI-2 channel ID 0 ○ RO CSI-2 signalling mode 0 ○ CSI_LANE_MODE RW CSI_lane_mode 0: Reserved, 1: 2-Lane, 2: Reserved, 3: 4-Lane 3 ○ TCLK_POST[8] RW Global Timing Parameters 0 TCLK_POST[7:0] RW Global Timing Parameters 6F THS_PREPARE[8] RW Global Timing Parameters 0 Index Byte Register Name RW 0x0110 [1:0] CSI_CH_ID RW 0x0111 [1:0] CSI_SIG_MODE 0x0114 [1:0] 0x0118 [0] 0x0119 [7:0]
IMX219PQH5-C 3-2-3 Frame Bank Control and Group “A” – [0x0150-0x018D] 3-2-3-1 Frame Bank Control Registers - [0x0150-0x0153] Index Byte Register Name ReTime Embd DL indicates frame bank applied in current frame X ○ defines Frame Bank to be applied in next frame (manual switching) 0 ○ XX ○ 0 ○ Comment [1] FRAME_BANK_STATUS RO-D [0] FRAME_BANK _ENABLE RW Default (HEX) RW 0x0150 0x0151 [7:0] 0x0152 [0] 0x0153 ― FRAME_BANK _FRM_CNT FRAME_BANK _FAST_TRACKING ― RO-D frame counter
IMX219PQH5-C Index Byte 0x0170 [2:0] Register Name RW X_ODD_INC_A RW 0x0171 [2:0] [0] 0x0172 Y_ODD_INC_A IMG_ORIENTATION_A[0] Re-Time Default (HEX) Embd DL x_odd_inc Increment for odd pixels 1, 3 frame bank 1 ○ y_odd_inc Increment for odd pixels 1, 3 frame bank 1 ○ image_orientation (for both direction) bit[0]: hori. direction bit[1]: vert.
IMX219PQH5-C 3-2-4 Frame Bank Control Group “B” – [0x0254-0x028D] 3-2-4-1 Frame Bank Registers Group “B”- [0x0254-0x028D] Index Byte Register Name RW 0x0254 [7:0] FRAME_DURATION_B RW 0x0255 [0] COMP_ENABLE_B RW 0x0256 ― 0x0257 [7:0] ANA_GAIN_GLOBAL_B 0x0258 [3:0] DIG_GAIN_GLOBAL_B[11:8] 0x0259 [7:0] DIG_GAIN_GLOBAL_B[7:0] [7:0] COARSE_INTEGRATION_ TIME_B[15:8] RW COARSE_INTEGRATION_ TIME_B[7:0] RW 0x025A ― 0x025B [7:0] 0x025C ― Reserved 0x025D [0] SENSOR_MODE_B 0x025E
IMX219PQH5-C Index Byte Register Name 0x028B [7:0] COARSE_INTEG_TIME_SHO RT_B [7:0] 0x028C [7:0] CSI_DATA_FORMAT_B [15:8] 0x028D [7:0] CSI_DATA_FORMAT_B [7:0] RW Comment RW CSI-2 data format Re-Time frame bank Default (HEX) Embd DL F4 ○ 0A ○ 0A ○ 3-2-5 Set-up Registers – [0x0300-0x0627] 3-2-5-1 Clock Set-up Registers – [0x0300-0x0313] Embd DL vt_pix_clk_div Video Timing Pixel Clock Divider Value 05 ○ RW vt_sys_clk_div Video Timing System Clock Divider Value 1 ○ RW pre_pll
IMX219PQH5-C 3-2-5-2 Flash Control (ERS) Registers – [0x0320-0x0338] Index Byte Register Name RW 0x0320 [0] FLASH_START_TRIG RW 0x0321 [0] FLASH_STATUS 0x0322 [7:0] FLASH_STROBE_DIV[7:0] 0x0324 [1:0] 0x032E [1:0] 0x032F [0] 0x0330 [7:0] Comment Re-Time Default (HEX) Flash strobe start trigger for ERS mode. 0 Flash status signal 0 RW Internal divider for checking timing of flash strobe. 01 FLASH_STROBE_ OUTPUT_ENABLE RW Flash strobe output enable.
IMX219PQH5-C 3-2-5-5 Test Pattern Registers – [0x0600-0x0627] Index Byte 0x0600 [0] Register Name RW 0x0601 [7:0] 0x0602 [1:0] TD_R[9:8] 0x0603 [7:0] TD_R[7:0] 0x0604 [1:0] TD_GR[9:8] RW 0x0605 [7:0] TD_GR[7:0] 0x0606 [1:0] TD_B[9:8] test_pattern_mode V-sync 0 test_data_red 0 test_data_greenR 00 0 RW 0x0607 [7:0] TD_B[7:0] 0x0608 [1:0] TD_GB[9:8] 0x0609 [7:0] TD_GB[7:0] 0x060A [7:0] H_CUR_WIDTH[15:8] test_data_blue 00 0 RW test_data_greenB 00 0 RW 0x060B [7:0] H_
IMX219PQH5-C 3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static) 3-3-1 Integration Time and Gain Parameter Limit Registers – [0x1000-0x1301] 3-3-1-1 Integration Time Parameter Limit Registers – [0x1000-0x1007] Index Byte 0x1000 ― 0x1001 [0] 0x1002 ― 0x1003 ― 0x1004 [7:0] Register Name integration_time_capability 0x1005 [7:0] 0x1006 [7:0] 0x1007 [7:0] RW RO Reserved RO coarse_integration_time_min RO Comment Re-Time 0 – coarse integration but NO fine integration
IMX219PQH5-C 3-3-1-3 Pre-PLL and PLL Clock Set-up Capability Registers – [0x1100-0x111F] Index Byte 0x1100 [7:0] 0x1101 Register Name [7:0] 0x1102 [7:0] 0x1103 [7:0] 0x1104 [7:0] 0x1105 [7:0] 0x1106 [7:0] 0x1107 [7:0] 0x1108 [7:0] [7:0] [7:0] [7:0] 0x110C [7:0] (HEX) RO Minimum external clock frequency Format: IEEE 32-bit float Units: MHz 6 MHz ( = min_ext_clk_freq_mhz) C0 00 RO Maximum external clock frequency Format: IEEE 32-bit float Units: MHz 27 MHz ( = max_ext_clk_freq_mhz
IMX219PQH5-C 3-3-1-4 Read Domain Clock Set-up Capability Registers – [0x1120-0x1137] Index Byte 0x1120 [7:0] Register Name min_vt_sys_clk_div 0x1121 [7:0] 0x1122 [7:0] max_vt_sys_clk_div 0x1123 [7:0] 0x1124 [7:0] 0x1125 RW RO RO Comment Re-Time Default (HEX) Minimum video timing system clock divider value Format: 16-bit unsigned integer 00 Maximum video timing system clock divider value Format: 16-bit unsigned integer 00 01 02 43 [7:0] min_vt_sys_clk_freq_mhz RO Minimum video ti
IMX219PQH5-C 3-3-1-5 Frame Timing Parameter Limit Registers – [0x1140-0x114B] Index Byte 0x1140 [7:0] 0x1141 [7:0] 0x1142 [7:0] 0x1143 [7:0] 0x1144 [7:0] 0x1145 [7:0] 0x1146 [7:0] Register Name min_frame_length_ lines RO max_frame_length_ lines RO min_line_length_pck RO max_line_length_pck 0x1147 [7:0] 0x1148 [7:0] min_line_blanking_pck 0x1149 [7:0] 0x114A [7:0] min_frame_blanking_lines 0x114B RW RO RO RO [7:0] Comment Re-Time Minimum Frame Length allowed.
IMX219PQH5-C 3-3-1-7 Image Size Parameter Limit Registers – [0x1180-0x118F] Index Byte 0x1180 [7:0] Register Name x_addr_min 0x1181 [7:0] 0x1182 [7:0] 0x1183 [7:0] 0x1184 [7:0] RO y_addr_min RO x_addr_max 0x1185 [7:0] 0x1186 [7:0] RO y_addr_max 0x1187 [7:0] 0x1188 [7:0] RO min_x_output_size 0x1189 [7:0] 0x118A [7:0] min_y_output_size 0x118B [7:0] 0x118C [7:0] 0x118D [7:0] 0x118E [7:0] 0x118F [7:0] RW max_x_output_size max_y_output_size RO RO RO Comment Re-Time
IMX219PQH5-C 3-4 Manufacturer Specific Registers – [0x3000-0x5FFF] To access this address area, it is necessary to send command sequence as below. Table 11 Access command sequence Seq. No.
IMX219PQH5-C Index (HEX) Bit Register Name RW Comment Re-Timed Default (HEX) 3221 [7:0] OTPIF_DT_29 RW otpif_data_29 00 3222 [7:0] OTPIF_DT_30 RW otpif_data_30 00 3223 [7:0] OTPIF_DT_31 RW otpif_data_31 00 3224 [7:0] OTPIF_DT_32 RW otpif_data_32 00 3225 [7:0] OTPIF_DT_33 RW otpif_data_33 00 3226 [7:0] OTPIF_DT_34 RW otpif_data_34 00 3227 [7:0] OTPIF_DT_35 RW otpif_data_35 00 3228 [7:0] OTPIF_DT_36 RW otpif_data_36 00 3229 [7:0] OTPIF_DT_37 RW otpif
IMX219PQH5-C 3-5 Frame Bank A and Bank B specific output samples Specific output examples are shown on the following pages.
IMX219PQH5-C Addr (Hex) Register Name in Byte (Hex) Addr (Hex) Register Name in Byte (Hex) 0x0143 READOUT_V_CNT[7:0] XX 0x0143 READOUT_V_CNT[7:0] XX 0x0150 [0]: FRAME_BANK_ENABLE XX 0x0150 [0]: FRAME_BANK_ENABLE XX 0x0151 FRAME_BANK _FRM_CNT XX 0x0151 FRAME_BANK _FRM_CNT XX 0x0152 FRAME_BANK _FAST_TRACKING XX 0x0152 FRAME_BANK _FAST_TRACKING XX Line2 (Embedded Data Line) Line2 (Embedded Data Line) 0x0154 FRAME_DURATION_A XX 0x0254 FRAME_DURATION_B XX 0x0155 COMP_ENABL
IMX219PQH5-C Addr (Hex) Register Name in Byte (Hex) Addr (Hex) Register Name in Byte (Hex) 0x0177 BINNING_ CAL_MODE_V_A XX 0x0277 BINNING_ CAL_MODE_V_B XX 0x0188 RESERVE XX 0x0288 RESERVE XX 0x0189 ANA_GAIN_GLOBAL_SHORT_A XX 0x0289 ANA_GAIN_GLOBAL_SHORT_B XX 0x018A COARSE_INTEG_TIME_SHORT_A [15:8] XX 0x028A COARSE_INTEG_TIME_SHORT_B [15:8] XX 0x018B COARSE_INTEG_TIME_SHORT_A [7:0] XX 0x028B COARSE_INTEG_TIME_SHORT_B [7:0] XX 0x018C CSI_DATA_FORMAT_A [15:8] XX 0x028C
IMX219PQH5-C Addr (Hex) Register Name in Byte (Hex) Addr (Hex) Register Name in Byte (Hex) 0x030B OPSYCK_DIV XX 0x030B OPSYCK_DIV XX 0x030C PLL_OP_MPY[10:8] XX 0x030C PLL_OP_MPY[10:8] XX 0x030D PLL_OP_MPY[7:0] XX 0x030D PLL_OP_MPY[7:0] XX 0x030E RESERVE XX 0x030E RESERVE XX 0x0318 RESERVE XX 0x0318 RESERVE XX 0x0319 RESERVE XX 0x0319 RESERVE XX 0x031A RESERVE XX 0x031A RESERVE XX 0x031B RESERVE XX 0x031B RESERVE XX 0x031C RESERVE XX 0x031C RESERVE
IMX219PQH5-C 4. Output Data Format 4-1 CSI-2 Output Data Format 4-1-1 CSI-2 Output Data Channels The IMX219PQH5-C can select the CSI-2 2 lanes or CSI-2 4 lanes serial signal output method that uses all pairs of differential signals for image data output.
IMX219PQH5-C Line Blanking Clock Lane Disconnect Terminator Data Lane LP-11 LP-01 LP-00 Fig. 21 Signaling Waveform during Line Blanking Period (CSI-2) Frame Blanking Clock Lane Disconnect Terminator Data Lane LP-11 LP-01 LP-00 Fig.
IMX219PQH5-C 4-1-4 Data type Data types of each line are shown as below. Table 13 Image pixel area and data type image pixel area Data Type Embedded Data Lines Embedded Data OBside ineffective area Null OB area for internal use Null effective OB OPB Data Effective area side ineffective area Null effective pixel RAW10 or RAW8 or COMP8 4-1-5 CSI-2 Frame Format The data format of each line is based on CSI-2 General Frame Format.
IMX219PQH5-C 4-1-6 CSI-2 Embedded Data Line The value of the 2-wire serial communication configuration register can be output at the start of the frame. The output register is indicated in the “Embd DL” column of the 2-wire serial communication Register Map. The Embedded data line is output in the two lines following the sync code FS. FS PH Embedded Data Lines PF Packet Header Pixels (effective pixels) Packet Footer FE Fig.
IMX219PQH5-C The end of the address and register value is determined according to the tags embedded in the data. Table 15 Embedded Data Line Tag Tag Data Byte Description 00h Illegal Tag.
IMX219PQH5-C 5. Setting Required for Imaging 5-1 Pixel Array Physical Image Pixel array physical image is shown below. It is the pixel array when upper right corner of the physical image is Pin 1. The IMX219PQH5-C has vertical OB area, which cannot read out. Readout position is explained by Readout Position session Invalid Active area （8） InValid Active Area (8) OPB Invalid Area（16） Effective OPB（16） OPB Invalid Area （8） Fig.
IMX219PQH5-C 5-2 Pixel Binning Mode Binning read-out can be used to obtain an image of lower resolution for full field of view. It has advantage on frame rate than using digital scaling, and on signal-to-noise ratio than using sub-sampling. See Binning Capability Registers, for detail of available configurations. The following diagram describes on 2x2 averaged binning operations. Pixels of two adjacent rows and columns are averaged, and read out as one output pixel.
IMX219PQH5-C 5-3 image size The relation of image output size and the register is shown below. Fig.
IMX219PQH5-C 5-4 Readout Position The IMX219PQH5-C default status is readout from the lower left corner when Pin 1 is located in the upper right corner. The image is inverted vertically and horizontally by the lens, so proper image output results when Pin 1 is located in the upper right corner. 1PIN F F Lens image_orientation=0h Fig. 30 Readout Position Readout direction can be set by the registers.
IMX219PQH5-C 5-5 Frame Rate Calculation Formula Frame rate in all-pixel scan mode is calculated by the followings.
IMX219PQH5-C 5-7-2 Storage Time Calculation Method The storage time (TSH) can be obtained from the following equation. TSH = ( Coarse_Integration_Time × ime Per Line ) + (α pix_clk_period = 1/Pix_Clock_Freq [MHz] pix clk period ) Where α = offset time = readdable from fine_integration_time register and obtained from the following equation.
IMX219PQH5-C 5-8 Gain Settings Analogue gain and digital gain can be set independently. Analogue Gain Settings Only global analogue gain is supported. The analogue gain is set by the following equation. Gain analogue (m0 X + c0) (m1 X + c1) The variables are shown in the table below.
IMX219PQH5-C ANA_GAIN_GLOBAL Gain(times) Gain(dB) ANA_GAIN_GLOBAL Gain(times) Gain(dB) 0.00 0.03 0.07 0.10 0.14 0.17 0.21 0.24 0.28 0.31 0.35 0.38 0.42 0.45 0.49 0.52 0.56 0.60 0.63 0.67 0.71 0.74 0.78 0.82 0.86 0.89 0.93 0.97 1.01 1.04 1.08 1.12 1.16 1.20 1.24 1.28 1.32 1.36 1.40 1.44 1.48 1.52 1.56 1.60 1.64 1.68 1.72 1.76 1.80 1.85 1.89 1.93 1.97 2.01 2.06 2.10 2.14 2.19 2.23 2.28 2.32 2.36 2.41 2.
IMX219PQH5-C 5-8-2 Digital gain settings The IMX219PQH5-C can set the digital gain for global. The registers required to set the digital gain are as follows.
IMX219PQH5-C dec 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 hex 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 dec 255 5 11 17 23 29 35 42 48 55 61 68 74 81 88 95 102 109 116 124 131 138 146 154 161 169 177 185 193 201 210 218 226 235 244 252 5 14 23 32 42 51 60 70 80 90 99 109 120 130 140 151 161 172 183 194 205 217 228 239 hex FF 5 B 11 17 1D 23 2A 30 37
IMX219PQH5-C 6. On Chip Image Processing Data flow of our “On-Chip Image Processing” is written in following figure. A/D-converted digital signal is input, and processed data is asserted from CSI-2. Analogue Domain Test Pattern Generator Defect Correction Digital Gain Setting default mode Pixel Re-align In H direction Black Level Adjust FIFO Fig. 32 Data Flow Diagram 6-1 Test Pattern Generator The IMX219PQH5-C can output test signals using the internal pattern generator.
IMX219PQH5-C Table 26 Description of Test Pattern Registers Address Name Description 0x0600 0000h– no pattern (default) 0001h – solid color 0002h – 100 % color bars 0003h – fade to grey color bar 0004h – PN9 0005h – 16 split color bar 0006h – 16 split inverted color bar 0007h – column counter 0008h – inverted column counter 0009h – PN31 test_pattern_mode 0x0601 0x0602 TD_R[9:8] 0x0603 TD_R[7:0] 0x0604 TD_GR[9:8] 0x0605 TD_GR[7:0] 0x0606 TD_B[9:8] 0x0607 TD_B[7:0] 0x0608 TD_GB[9:8] 0x060
IMX219PQH5-C 6-1-1-1 Pattern Description Table 27 Description of Test Patterns 100 % color bar test_pattern_mode = 0002h Embedded data line fade to gray color bar test_pattern_mode = 0003h Embedded data line 64
IMX219PQH5-C 16 split Color Bar Chart test_pattern_mode = 0005h Embedded data line Inversed 16 split Color Bar Chart test_pattern_mode = 0006h Embedded data line 65
IMX219PQH5-C column counter test_pattern_mode = 0007h Embedded data line inverted column counter test_pattern_mode = 0008h Embedded data line 66
IMX219PQH5-C 6-2 Digital Gain Setting See Digital gain settings section. 6-3 Black Level Adjust The register required to set the Black Level Adjust is as follows. Table 28 Black Level Adjust Setting Register Index (HEX) Bit D1EA [1:0] Register Name DT_PEDESTAL[9:8] RW Comment Default (HEX) Re-Timed RW 0 Set Black Level D1EB [7:0] DT_PEDESTAL[7:0] RW 40 6-4 Defect Correction The registers required to set the Defect Correction are as follows.
IMX219PQH5-C 0x0274 [0] BINNING_MODE_H_B RW defines binning mode (H-direction). 0: no-binning, 1: x2-binning 2: x4-binning 3: x2 analog (special) binning Frame Bank 0 ○ Re-Time Default (HEX) Embd DL Frame Bank 00 ○ Frame Bank 00 ○ Frame Bank 09 ○ Frame Bank 9F ○ 6-6 Pixel Re-alignment V Direction The registers required to set the Pixel Re-alignment H Direction are as follows.
IMX219PQH5-C 7. NVM Memory Map 7-1 Block Diagram CCI NVM Access Control (ECC) Control Block NVM Pipeline Pixel Controller Fig. 33 Block Diagram NVM is composed of 12 pages (from 0 to 11) and 64 bytes per page. ECC is also applied for every 16 address (bytes), 4 rows in 1 page. Fig. 34 NVM Map structure 7-2 NVM Functions NVM block has following functions. Table 31 Functions via NVM No Item Description 1 Data Interface User can write/read data via CCI by the unit of page 2 Writing Reg.
IMX219PQH5-C 6 ECC status Can check while reading/writing that ECC is applied by page. 1. Read data is correct. No ECC is applied. 2. Read data is correct with 1-bit correction of ECC. 3. Read data is incorrect though ECC is applied (means >2 bits per a unit of 16-byte (row) are incorrect).
IMX219PQH5-C OTP controller does NOT clear previous values automatically. 5. Set last byte of OTP buffer 0x3243 need to write again with same value of step4 6. Wait write sequence finish ( >12.8msec:target [25µs /bit] x 8 bit x 16btye x 4row) 7. Repeat the above (3) – (6) sequence again for twice write process. Then when reading; 1. Set controller “ECC ON” or “ECC OFF” by 0x3300 = 00h (ECC ON), 08h (ECC OFF) ; 2. Set Read by 0x3200 = "1h." 3. Set page from 0 to 11 by 0x3202. 4.
IMX219PQH5-C 7-4 NVM Memory Map Table 33 NVM Memory capacity Capacity data Owner 768 byte Total 672 byte Integrator 96 byte Sony Table 34 NVM Memory Map Example Page (dec) Row (dec) Addr (hex) 0 0-3 000 - 03F Integrator 1 4-7 040 - 07F Integrator 2 8-11 080 - 0BF Integrator 3 12-15 0C0 - 0FF Integrator 4 16-19 100 - 13F Integrator 5 20-23 140 - 17F Integrator 6 24-27 180 - 1BF Integrator 7 28-31 1C0 - 1FF Integrator 8 32-35 200 - 23F Integrator 9 36-39 240 -
IMX219PQH5-C Page (dec) Row (dec) Addr (hex) Category Name 10 43 2B2 please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 address Sony 10 43 2B3 please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 address Sony 10 43 2B4 please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 address Sony 10 43 2B5 please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 addres
IMX219PQH5-C Page (dec) Row (dec) Addr (hex) Category Name 11 44 2CE please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 address Sony 11 44 2CF please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 address Sony 11 45 2D0 please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 address Sony 11 45 2D1 please don't write Defect address (single, 2 adjacent in same color , 2x4 static),10 addres
IMX219PQH5-C 7-5 Defects Address registration The single defect, the same color adjoining (SCA) defect and 2 x 4 defect are stored into NVM and corrected. 7-5-1 Single defect address 1. Target Address; (x, y) = (xt, yt) *Output area is Effective Area Output size is 3280x2464 (0,0) - (3279,2463) x = image area address + offset; offset = 8d y = image area address + offset; offset = 48d (not include embedded lines) Scan Direction Image Orientation = 0d Starting Red Pixel Data x Fig.
IMX219PQH5-C 7-5-4 Example Setting Example when defect addr are 1st: (228d, 522d), func: adjoin, dir: 1 2nd: (2846d, 1460d), func: 2x4 3rd: (26d, 20d), single → Offset values are (physical address) 1st: (236d, 570d) , func: adjoin, SRC = 2, DIR = 1, H_ADR = ECh, V_ADR = 23Ah 2nd: (2854d, 1508d) , func:2x4 SRC = 3, DIR = 0, H_ADR = B26h, V_ADR = 5E4h 3rd: (34d, 68d), func: single SRC = 1, DIR = 0, H_ADR = 22h, V_ADR = 44h Table 35 Example setting of defect pixel Addr (hex) description Value (hex) 2A0 D
IMX219PQH5-C 8. How to operate IMX219PQH5-C 8-1 Power on sequence Power on sequence of IMX219PQH5-C is below figure. Startup Sequence in 2-wire Serial Communication Mode Perform power-on according to the following sequence. The XCLR pin must be released (Low → High) after all the power supplies (VANA,VDIG,VDDL) are completed. Power Off Software Standby Hardware Standby Streaming (Active) t0 VANA t1 VDIG VDDL (1.
IMX219PQH5-C Table 36 Operation Specifications 2-wire Serial Communication Mode Constraint Sequence free of VDDs rising Label t0, t1, t2 Min. Max. Units VANA, VDIG, VDDL may rise in any order. ns ― µs 200 µs 6 ― ms t6 ― 32000 clocks D-PHY power-up t7 1 1.1 ms D-PHY init t8 100 110 µs After releasing software standby to data streaming time t9 1.
IMX219PQH5-C 8-2 Power off sequence Perform the power-off in the sequence shown below. Streaming (Active) Hardware Standby Software Standby Power Off VBAT VANA t3 VDIG t4 VDDL t5 INCK XCLR t1 XCLR (internal) t2 t0 CCI CLK +/- LP11 LP00 Data 1 &2 +/- LP11 LP00 Data 3 & 4 +/- LP11 LP00 Fig.
IMX219PQH5-C To in power-off sequence varies depending on the CCI communication end timing as shown below. 1. When the CCI communication is performed with Software Standby between SOF and EOF, all communicated frame data is output and the status is converted to Software Standby. Enter Stop SDA SCL CSI2 DATA S O F Frame Counter E O F N 0xFF Frame_length_lines Fig. 41 Software Standby Operation Pattern 1 2.
IMX219PQH5-C 9. Other Functions 9-1 Clock System 9-1-1 Clock Structure The IMX219PQH5-C clock system has the following structure.
IMX219PQH5-C 9-2 Clock Setting Example Interface CSI-2 CSI-2 CSI-2 10 10 10 Raw10 Raw10 Raw10 30 frame/s 180 frame/s 21 frame/s (*１) 4 4 2 Full-Pel 2 (V) X2 (H) analog (special) binning Full-Pel 3280 x 2464 1408 x 792 3280 x 2464 702 MHz 702 MHz 456 MHz EXCK_FREQ 12 12 12 VTSYCK_DIV 1 1 1 vt_pix_clk_div 5 5 10 Pix Rate 280.8M pix 280.8M pix 182.4M pix Actual freq (VTCK) 140.4 MHz 140.4 MHz 91.
IMX219PQH5-C 9-3 Temperature Sensor Registers to be related about temperature sensor are the followings. Table 40 Temperature setting registers Index Re-Time Default Byte Register Name RW Comment [7] TEMPERATURE_EN RW start register to measure sensor temperature 0 [6:0] TEMPERATURE_VAL RO-D result of measurement of sensor temperature 00 (HEX) Embd DL Comments 0x0140 The temperature sensor measures the junction temperature of the sensor silicon.
IMX219PQH5-C 10. Electrical Characteristics 10-1 Absolute Maximum Ratings Table 41 Absolute Maximum Ratings Item Symbol Min. Supply voltage (analogue) VANA Supply voltage (Core) Typ. Max. Unit Remarks -0.3 3.3 V VDDL -0.3 2.0 V Supply voltage (IF) VDIG -0.3 3.3 V Input voltage VI -0.3 3.3 V Output voltage VO -0.3 3.
IMX219PQH5-C 10-3 Electrical Characteristics Table 43 DC Characteristics Item Pins Symbol Min. Typ. Max. Unit VANA 2.6 2.8 3.0 V VDIG 1.62 1.8 1.98 V VDDL 1.08 1.20 1.30 V VIL -0.5 0.3VDIG V SCL, SDA, VIH 0.7VDIG VDIG + 0.5 V GPO VOL 0.25VDIG V VDDHFIL1,2 VDDHCM1,2 VDDHAN VDDHPL Supply voltage VDDHSN1,2 VDDMCO VDDLSC1-8 VDDLCN1,2 VDDLIO1,2 Digital input/output voltage VOH Digital output voltage FSTROBE VOL VOH Digital input voltage 0.75VDIG V 0.45 V V VDIG - 0.
IMX219PQH5-C 10-4 AC Characteristics 10-4-1 Master Clock Waveform Diagram 10-4-1-1 INCK Square Waveform Input Specifications Input specifications are shown below when square-wave inputs directly into the external pin INCK. fRIS fFA E LL 0.65VDIG 0.5VDIG 0.35VDIG tp Fig. 44 Master Clock Square Waveform Diagram Table 44 Master Clock Square Waveform Input Characteristics Item Symbol Min. Typ. Max.
IMX219PQH5-C 11. Spectral Sensitivity Characteristic (Neither lens characteristics nor light source characteristics is included.) Fig.
IMX219PQH5-C 12. Image Sensor Characteristics 12-1 Image Sensor Characteristics Table 46 Image Sensor Characteristics (30 frame/s, VANA = 2.8 V, VDIG = 1.2 V, VIF = 1.8 V, Tj = 60 ˚C) Item Symbol Min. Typ. Max. Unit Range Measur ement method LSB Center 1 Center 2 LSB Zone1 3 Remarks S 205 RG 0.45 0.51 0.57 BG 0.40 0.46 0.52 Saturation signal Vsat 1023 Video signal shading SH 70 % Zone2D 4 Design assurance Dark signal Vdt 0.
IMX219PQH5-C 13. Measurement Method for Image Sensor Characteristics 13-1 Measurement conditions The device operation conditions are at the typical values of the bias and clock voltage. Table 47 Measurement Conditions Supply voltage Analog 2.8 V, digital 1.2 V, IF 1.
IMX219PQH5-C 13-4 Measurement method Sensitivity Set the measurement condition to the standard imaging condition I. After setting the luminous intensity of 10 times that of the standard imaging condition and the electronic shutter mode with a shutter speed of 1/150 s, measure the Gr and Gb signal outputs (VGr, VGb) at the center of imaging area, and substitute the values into the following formula.
IMX219PQH5-C 14. Spot Pixel Specification Table 48 Spot Pixel Specifications (15 frame/s, VANA = 2.8 V, VDIG = 1.2 V, VIF = 1.8 V, Tj = 60 ˚C) Maximum distorted pixels in each zone Type of distortion Level Note 1) Zone2D Zone3 Ineffective OB Effective OB Measurement method Black or white pixels at high light 30 % ≤ D 40 No evaluation criteria applied 2 White pixels in the dark 28 (LSB) ≤ D 600 No evaluation criteria applied 2 Note) 1. 2. 3. Remarks 1/30 s storage Note 2) D...
IMX219PQH5-C 15. Notice on White Pixels Specifications After shipment inspection of CMOS image sensors, pixels of CMOS image sensors may be distorted and then distorted pixels may cause white point effects in dark signals in picture images. (Such white point effects shall be hereinafter referred to as "White Pixels.") Cosmic radiation is one of the causes of White Pixels. Unfortunately, it is not possible with current scientific technology for CMOS image sensors to prevent such distorted pixels.
IMX219PQH5-C 15-1 Measurement Method for Spot Pixels Measure under the standard imaging condition II. 15-2 Spot Pixel Pattern Specifications Black or white pixels at high light After adjusting the average value of the Gr/Gb signal output to 333 [LSB], measure the local dip point (black pixel at high light, VXB) and peak point (white pixel at high light, VXK) in the Gr/Gb signal output Vx (x = Gr/Gb), and substitute the values into the following formula. Fig.
IMX219PQH5-C 16. Chief Ray Angle Characteristics IMX219 CRA 40 Angle ［°］ 30 20 10 0 0 10 20 30 40 50 60 70 Image Height ［%］ 80 Fig.
IMX219PQH5-C 17. Connection Example VanaVdigVddl 2.2 µF 2.2 µF 0.22 µF VSSLSC4 POREN XCLR TENABLE GPO FSTROBE SDA NC Chip center (0,0) VDDHCM1 VSSLSC1 VSSLCN1 VSSHCM1 VSSLSC2 VSSLDM1 VDDLCN1 VDDHFIL1 VDDLCN2 VSSLCN2 1.0 µF VSSHCM2 VCP VBO VSSHSN1 VDDHSN1 2.
IMX219PQH5-C 18. Notes On Handling 1. Static charge prevention Image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. (1) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. (2) Use a wrist strap when handling directly. (3) Install grounded conductive mats on the floor and working table to prevent the generation of static electricity.
