RP2040 Datasheet Colophon Copyright © 2020 Raspberry Pi (Trading) Ltd. The documentation of the RP2040 microcontroller is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International (CC BY-ND). Portions Copyright © 2019 Synopsys, Inc. All rights reserved. Used with permission. Synopsys & DesignWare are registered trademarks of Synopsys, Inc. Portions Copyright © 2000-2001, 2005, 2007, 2009, 2011-2012, 2016 ARM Limited. All rights reserved. Used with permission.
RP2040 Datasheet expand or otherwise modify RPTL’s Standard Terms including but not limited to the disclaimers and warranties expressed in them.
RP2040 Datasheet Table of Contents Colophon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Legal Disclaimer Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RP2040 Datasheet 2.9.3. On-Chip Voltage Regulator Input Supply (VREG_VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.4. USB PHY Supply (USB_VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.5. ADC Supply (ADC_AVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.6.
RP2040 Datasheet 2.17.6. ROSC Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.17.7. DORMANT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.17.8. List of Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RP2040 Datasheet 3.6. Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1. Duplex SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2. WS2812 LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RP2040 Datasheet 4.6.5. List of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7. Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RP2040 Datasheet Bootrom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RP2040-E9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RP2040 Datasheet Chapter 1. Introduction Microcontrollers connect the world of software to the world of hardware. They allow developers to write software which interacts with the physical world in the same deterministic, cycle-accurate manner as digital logic. They occupy the bottom left corner of the price/performance space, outselling their more powerful brethren by a factor of ten to one. They are the workhorses that power the digital transformation of our world.
RP2040 Datasheet 1. Number of processor cores (2) 2. Loosely which type of processor (M0+) 3. floor(log2(ram / 16k)) 4. floor(log2(nonvolatile / 16k)) or 0 if no onboard nonvolatile storage see Figure 1. Figure 1. An explanation for the RP 2 0 4 0 name of the RP2040 chip. floor(log2(nonvolatile / 16k)) floor(log2(ram / 16k)) Type of core (e.g. M0+) Number of cores Raspberry Pi 1.2. Summary RP2040 is a low-cost, high-performance microcontroller device with flexible digital interfaces.
RP2040 Datasheet Figure 2. A system overview of the RP2040 chip Code may be executed directly from external memory through a dedicated SPI, DSPI or QSPI interface. A small cache improves performance for typical applications. Debug is available via the SWD interface. Internal SRAM can contain code or data. It is addressed as a single 264 kB region, but physically partitioned into 6 banks to allow simultaneous parallel access from different masters.
RP2040 Datasheet Figure 3. RP2040 Pinout for QFN-56 7x7mm (reduced ePad size) 1.4.2. Pin Descriptions Table 1. The function of each pin is briefly described here. Full electrical Name Description GPIOx General-purpose digital input and output. RP2040 can connect one of a number of internal peripherals to each GPIO, or control GPIOs directly from software. specifications can be found in Chapter 5. GPIOx/ADCy General-purpose digital input and output, with analogue-to-digital converter function.
RP2040 Datasheet Name Description USB_VDD Power supply for internal USB Full Speed PHY, nominal voltage 3.3 V ADC_AVDD Power supply for analogue-to-digital converter, nominal voltage 3.3 V VREG_VIN Power input for the internal core voltage regulator, nominal voltage 1.8 V to 3.3 V VREG_VOUT Power output for the internal core voltage regulator, nominal voltage 1.1 V, 100 mA max current DVDD Digital core power supply, nominal voltage 1.1 V.
RP2040 Datasheet Function Table 3.
RP2040 Datasheet Chapter 2. System Description This chapter describes the RP2040 key system features including processor, memory, how blocks are connected, clocks, resets, power, and IO. Refer to Figure 2 for an overview diagram. 2.1. Bus Fabric The RP2040 bus fabric routes addresses and data across the chip. Figure 4 shows the high-level structure of the bus fabric.
RP2040 Datasheet GB/s. The system address map has been arranged to make this parallel bandwidth available to as many software use cases as possible — for example, the striped SRAM alias (Section 2.6.2) scatters main memory accesses across four crossbar ports (SRAM0…3), so that more memory accesses can proceed in parallel. 2.1.1. AHB-Lite Crossbar At the centre of the RP2040 bus fabric is a 4:10 fully-connected crossbar.
RP2040 Datasheet NOTE Priority arbitration only applies to multiple masters attempting to access the same slave on the same cycle. Accesses to different slaves, e.g. different SRAM banks, can proceed simultaneously. When accessing a slave with zero wait states, such as SRAM (i.e. can be accessed once per system clock cycle), highpriority masters will never observe any slowdown or other timing effects caused by accesses from low-priority masters.
RP2040 Datasheet PERFSEL Event Description x 16 XIP_MAIN access, Completion of an access to the XIP_MAIN arbiter, which was previously delayed due contested to an access by another master. 17 XIP_MAIN access Completion of an access to the XIP_MAIN arbiter 18 ROM access, Completion of an access to the ROM arbiter, which was previously delayed due to an contested access by another master. ROM access Completion of an access to the ROM arbiter 19 2.1.2.
RP2040 Datasheet To update part of an IO register, without a read-modify-write sequence, the best solution on RP2040 is atomic set/clear/XOR (see Section 2.1.2). Note that this is more flexible than byte or halfword writes, as any combination of fields can be updated in one operation. Upon a 8-bit or 16-bit write (such as a strb instruction on the Cortex-M0+), an IO register will sample the entire 32-bit write databus.
RP2040 Datasheet Offset Name Info 0x04 BUS_PRIORITY_ACK Bus priority acknowledge 0x08 PERFCTR0 Bus fabric performance counter 0 0x0c PERFSEL0 Bus fabric performance event select for PERFCTR0 0x10 PERFCTR1 Bus fabric performance counter 1 0x14 PERFSEL1 Bus fabric performance event select for PERFCTR1 0x18 PERFCTR2 Bus fabric performance counter 2 0x1c PERFSEL2 Bus fabric performance event select for PERFCTR2 0x20 PERFCTR3 Bus fabric performance counter 3 0x24 PERFSEL3 Bus fabric
RP2040 Datasheet Description Bus fabric performance counter 0 Table 7. PERFCTR0 Register Bits Description Type Reset 31:24 Reserved. - - 23:0 Busfabric saturating performance counter 0 WC 0x000000 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0 BUSCTRL: PERFSEL0 Register Offset: 0x0c Description Bus fabric performance event select for PERFCTR0 Table 8. PERFSEL0 Register Bits Description Type Reset 31:5 Reserved.
RP2040 Datasheet Table 9. PERFCTR1 Register Bits Description Type Reset 31:24 Reserved. - - 23:0 Busfabric saturating performance counter 1 WC 0x000000 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1 BUSCTRL: PERFSEL1 Register Offset: 0x14 Description Bus fabric performance event select for PERFCTR1 Table 10. PERFSEL1 Register Bits Description Type Reset 31:5 Reserved. - - 4:0 Select an event for PERFCTR1.
RP2040 Datasheet Table 11. PERFCTR2 Register Bits Description Type Reset 31:24 Reserved. - - 23:0 Busfabric saturating performance counter 2 WC 0x000000 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2 BUSCTRL: PERFSEL2 Register Offset: 0x1c Description Bus fabric performance event select for PERFCTR2 Table 12. PERFSEL2 Register Bits Description Type Reset 31:5 Reserved. - - 4:0 Select an event for PERFCTR2.
RP2040 Datasheet Table 13. PERFCTR3 Register Bits Description Type Reset 31:24 Reserved. - - 23:0 Busfabric saturating performance counter 3 WC 0x000000 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3 BUSCTRL: PERFSEL3 Register Offset: 0x24 Description Bus fabric performance event select for PERFCTR3 Table 14. PERFSEL3 Register Bits Description Type Reset 31:5 Reserved. - - 4:0 Select an event for PERFCTR3.
RP2040 Datasheet AHB-Lite Peripherals 0x50000000 IOPORT Registers 0xd0000000 Cortex-M0+ internal registers 0xe0000000 2.2.2. Detail ROM: ROM_BASE 0x00000000 XIP: XIP_BASE 0x10000000 XIP_NOALLOC_BASE 0x11000000 XIP_NOCACHE_BASE 0x12000000 XIP_NOCACHE_NOALLOC_BASE 0x13000000 XIP_CTRL_BASE 0x14000000 XIP_SRAM_BASE 0x15000000 XIP_SRAM_END 0x15004000 XIP_SSI_BASE 0x18000000 SRAM.
RP2040 Datasheet RESETS_BASE 0x4000c000 PSM_BASE 0x40010000 IO_BANK0_BASE 0x40014000 IO_QSPI_BASE 0x40018000 PADS_BANK0_BASE 0x4001c000 PADS_QSPI_BASE 0x40020000 XOSC_BASE 0x40024000 PLL_SYS_BASE 0x40028000 PLL_USB_BASE 0x4002c000 BUSCTRL_BASE 0x40030000 UART0_BASE 0x40034000 UART1_BASE 0x40038000 SPI0_BASE 0x4003c000 SPI1_BASE 0x40040000 I2C0_BASE 0x40044000 I2C1_BASE 0x40048000 ADC_BASE 0x4004c000 PWM_BASE 0x40050000 TIMER_BASE 0x40054000 WATCHDOG_BASE 0x40058000 R
RP2040 Datasheet 0xd0000000 SIO_BASE Cortex-M0+ Internal Peripherals: 0xe0000000 PPB_BASE 2.3. Processor subsystem The RP2040 processor subsystem consists of two Arm Cortex-M0+ processors — each with its standard internal Arm CPU peripherals — alongside external peripherals for GPIO access and inter-core communication. Details of the Arm Cortex-M0+ processors, including the specific feature configuration used on RP2040, can be found in Section 2.4. Figure 6.
RP2040 Datasheet NOTE The SIO is not connected to the main system bus due to its tight timing requirements. It can only be accessed by the processors, or by the debugger via the processor debug ports. Figure 7. The singlecycle IO block contains memory- Core 0 Core 1 mapped hardware Single-cycle IO which the processors must be able to IOPORT IOPORT access quickly. The FIFOs and spinlocks CPUID 1 CPUID 0 support message passing and FIFO 0 to 1 synchronisation between the two cores.
RP2040 Datasheet IMPORTANT CPUID should not be confused with the Cortex-M0+ CPUID register (Section 2.4.4.1.1) on each processor’s internal Private Peripheral Bus, which lists the processor’s part number and version. 2.3.1.2. GPIO Control The processors have access to GPIO registers for fast and direct control of pins with GPIO functionality.
RP2040 Datasheet SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_gpio/include/hardware/gpio.h Lines 461 - 463 461 static inline void gpio_clr_mask(uint32_t mask) { 462 sio_hw->gpio_clr = mask; 463 } SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_gpio/include/hardware/gpio.h Lines 521 - 530 521 * sequences when driving GPIOs -- instead functions like gpio_put() should be 522 * used to atomically update GPIOs.
RP2040 Datasheet A status register, FIFO_ST, provides the following status signals: • Incoming FIFO contains data (VLD) • Outgoing FIFO has room for more data (RDY) • The incoming FIFO was read from while empty at some point in the past (ROE) • The outgoing FIFO was written to while full at some point in the past (WOF) Writing to the outgoing FIFO while full, or reading from the incoming FIFO while empty, does not affect the FIFO state. The current contents and level of the FIFO is preserved.
RP2040 Datasheet 26 // return 64 bit value so we can efficiently return both (note quotient must be read last) 27 ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET] 28 ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET] 29 bx lr NOTE Software is free to perform other non divider operations during these 8 cycles.
RP2040 Datasheet 2.3.1.6. Interpolator Each core is equipped with two interpolators (INTERP0 and INTERP1) which can accelerate tasks by combining certain preconfigured operations into a single processor cycle. Intended for cases where the pre-configured operation is repeated many times, this results in code which uses both fewer CPU cycles and fewer CPU registers in the time-critical sections of the code.
RP2040 Datasheet NOTE By sheer coincidence, the interpolators are extremely well suited to SNES MODE7-style graphics routines. For example, on each core, INTERP0 can provide a stream of tile lookups for some affine transform, and INTERP1 can provide offsets into the tiles for the same transform. 2.3.1.6.1. Lane Operations Figure 9.
RP2040 Datasheet 39 puts("Masking with sign extension:"); 40 interp_config_set_signed(&cfg, true); 41 for (int i = 0; i < 8; ++i) { 42 interp_config_set_mask(&cfg, i * 4, i * 4 + 3); 43 interp_set_config(interp0, 0, &cfg); 44 45 printf("Nibble %d: %08x\n", i, interp0->add_raw[0]); } 46 } The above example should print: ACCUM0 = 1234abcd Nibble 0: 0000000d Nibble 1: 000000c0 Nibble 2: 00000b00 Nibble 3: 0000a000 Nibble 4: 00040000 Nibble 5: 00300000 Nibble 6: 02000000 Nibble 7: 10000000 Maskin
RP2040 Datasheet PEEK0, POP1: 458, 125 PEEK0, POP1: 126, 458 PEEK0, POP1: 459, 126 PEEK0, POP1: 127, 459 PEEK0, POP1: 460, 127 PEEK0, POP1: 128, 460 PEEK0, POP1: 461, 128 2.3.1.6.2. Blend Mode Blend mode is available on INTERP0 on each core, and is enabled by the CTRL_LANE0_BLEND control flag.
RP2040 Datasheet 914 998 CTRL_LANE1_SIGNED controls whether BASE0 and BASE1 are sign-extended for this interpolation (this sign extension is required because the interpolation produces an intermediate product value 40 bits in size). CTRL_LANE0_SIGNED continues to control the sign extension of the lane 0 intermediate result in PEEK2, POP2 as normal. Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/interp/hello_interp/hello_interp.
RP2040 Datasheet 0x010003e0 Finally, in blend mode when using the BASE_1AND0 register to send a 16-bit value to each of BASE0 and BASE1 with a single 32-bit write, the sign-extension of these 16-bit values to full 32-bit values during the write is controlled by CTRL_LANE1_SIGNED for both bases, as opposed to non-blend-mode operation, where CTRL_LANE0_SIGNED affects extension into BASE0 and CTRL_LANE1_SIGNED affects extension into BASE1. Pico Examples: https://github.
RP2040 Datasheet 194 interp_config_set_mask(&cfg, 0, 29); 195 // ...so that the shifted value is correctly sign extended 196 interp_config_set_signed(&cfg, true); 197 interp_set_config(interp1, 0, &cfg); 198 199 interp1->base[0] = 0; 200 interp1->base[1] = 255; 201 202 for (int i = -1024; i <= 1024; i += 256) { 203 interp1->accum[0] = i; 204 205 printf("%d\t%d\n", i, (int) interp1->peek[0]); } 206 } This should print: -1024 0 -768 0 -512 0 -256 0 0 0 256 64 512 128 768 19
RP2040 Datasheet 162 cfg = interp_default_config(); 163 interp_config_set_shift(&cfg, uv_fractional_bits - 8); 164 interp_config_set_signed(&cfg, true); 165 interp_config_set_cross_input(&cfg, true); // signed blending 166 interp_set_config(interp0, 1, &cfg); 167 168 int16_t samples[] = {0, 10, -20, -1000, 500}; 169 170 // step is 1/4 in our fractional representation 171 uint step = (1 << uv_fractional_bits) / 4; 172 173 interp0->accum[0] = 0; // initial sample_offset; 174 interp0->base[
RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/interp/hello_interp/hello_interp.
RP2040 Datasheet 264 for (uint i = 0; i < 12; i++) { 265 266 printf("0x%02x\n", output[i]); } 267 } This should print: 0x00 0x00 0x01 0x01 0x12 0x12 0x13 0x23 0x20 0x20 0x31 0x31 2.3.1.7. List of Registers The SIO registers start at a base address of 0xd0000000 (defined as SIO_BASE in SDK). Table 16.
RP2040 Datasheet Offset Name Info 0x050 FIFO_ST Status register for inter-core FIFOs (mailboxes).
RP2040 Datasheet Offset Name Info 0x0d4 INTERP1_POP_LANE0 Read LANE0 result, and simultaneously write lane results to both accumulators (POP). 0x0d8 INTERP1_POP_LANE1 Read LANE1 result, and simultaneously write lane results to both accumulators (POP). 0x0dc INTERP1_POP_FULL Read FULL result, and simultaneously write lane results to both accumulators (POP). 0x0e0 INTERP1_PEEK_LANE0 Read LANE0 result, without altering any internal state (PEEK).
RP2040 Datasheet Offset Name Info 0x158 SPINLOCK22 Spinlock register 22 0x15c SPINLOCK23 Spinlock register 23 0x160 SPINLOCK24 Spinlock register 24 0x164 SPINLOCK25 Spinlock register 25 0x168 SPINLOCK26 Spinlock register 26 0x16c SPINLOCK27 Spinlock register 27 0x170 SPINLOCK28 Spinlock register 28 0x174 SPINLOCK29 Spinlock register 29 0x178 SPINLOCK30 Spinlock register 30 0x17c SPINLOCK31 Spinlock register 31 SIO: CPUID Register Offset: 0x000 Description Processor core ide
RP2040 Datasheet Description GPIO output value Table 20. GPIO_OUT Register Bits Description Type Reset 31:30 Reserved. - - 29:0 Set output level (1/0 → high/low) for GPIO0…29. RW 0x00000000 Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
RP2040 Datasheet Table 24. GPIO_OE Register Bits Description Type Reset 31:30 Reserved. - - 29:0 Set output enable (1/0 → output/input) for GPIO0…29. RW 0x00000000 Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
RP2040 Datasheet Table 28. GPIO_HI_OUT Register Bits Description Type Reset 31:6 Reserved. - - 5:0 Set output level (1/0 → high/low) for QSPI IO0…5. RW 0x00 Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
RP2040 Datasheet Table 32. GPIO_HI_OE Register Bits Description Type Reset 31:6 Reserved. - - 5:0 Set output enable (1/0 → output/input) for QSPI IO0…5. RW 0x00 Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
RP2040 Datasheet Table 36. FIFO_ST Register Bits Name Description Type Reset 31:4 Reserved. - - - 3 ROE Sticky flag indicating the RX FIFO was read when empty. WC 0x0 WC 0x0 RO 0x1 RO 0x0 This read was ignored by the FIFO. 2 WOF Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. 1 RDY Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data) 0 VLD Value is 1 if this core’s RX FIFO is not empty (i.e.
RP2040 Datasheet Table 41. DIV_UDIVISOR Register Bits Description Type Reset 31:0 Divider unsigned divisor RW 0x00000000 Write to the DIVISOR operand of the divider, i.e. the q in p / q. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. SIO: DIV_SDIVIDEND Register Offset: 0x068 Table 42.
RP2040 Datasheet Table 45. DIV_REMAINDER Register Bits Description Type Reset 31:0 Divider result remainder RW 0x00000000 The result of DIVIDEND % DIVISOR (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
RP2040 Datasheet Table 49. INTERP0_BASE0 Register Bits Description Type Reset 31:0 Read/write access to BASE0 register. RW 0x00000000 SIO: INTERP0_BASE1 Register Offset: 0x08c Table 50. INTERP0_BASE1 Register Bits Description Type Reset 31:0 Read/write access to BASE1 register. RW 0x00000000 SIO: INTERP0_BASE2 Register Offset: 0x090 Table 51. INTERP0_BASE2 Register Bits Description Type Reset 31:0 Read/write access to BASE2 register.
RP2040 Datasheet Table 56. INTERP0_PEEK_LANE 1 Register Bits Description Type Reset 31:0 Read LANE1 result, without altering any internal state (PEEK). RO 0x00000000 SIO: INTERP0_PEEK_FULL Register Offset: 0x0a8 Table 57. INTERP0_PEEK_FULL Register Bits Description Type Reset 31:0 Read FULL result, without altering any internal state (PEEK). RO 0x00000000 SIO: INTERP0_CTRL_LANE0 Register Offset: 0x0ac Description Control register for lane 0 Table 58.
RP2040 Datasheet Bits Name Description Type Reset 15 SIGNED If SIGNED is set, the shifted and masked accumulator RW 0x0 RW 0x00 RW 0x00 RW 0x00 value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
RP2040 Datasheet Table 60. INTERP0_ACCUM0_AD D Register Bits Description Type Reset 31:24 Reserved. - - 23:0 Values written here are atomically added to ACCUM0 RW 0x000000 Reading yields lane 0’s raw shift and mask value (BASE0 not added). SIO: INTERP0_ACCUM1_ADD Register Offset: 0x0b8 Table 61. INTERP0_ACCUM1_AD D Register Bits Description Type Reset 31:24 Reserved.
RP2040 Datasheet Table 66. INTERP1_BASE1 Register Bits Description Type Reset 31:0 Read/write access to BASE1 register. RW 0x00000000 SIO: INTERP1_BASE2 Register Offset: 0x0d0 Table 67. INTERP1_BASE2 Register Bits Description Type Reset 31:0 Read/write access to BASE2 register. RW 0x00000000 SIO: INTERP1_POP_LANE0 Register Offset: 0x0d4 Table 68.
RP2040 Datasheet Table 73. INTERP1_PEEK_FULL Register Bits Description Type Reset 31:0 Read FULL result, without altering any internal state (PEEK). RO 0x00000000 SIO: INTERP1_CTRL_LANE0 Register Offset: 0x0ec Description Control register for lane 0 Table 74. INTERP1_CTRL_LANE 0 Register Bits Name Description Type Reset 31:26 Reserved. - - - 25 OVERF Set if either OVERF0 or OVERF1 is set. RO 0x0 24 OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set.
RP2040 Datasheet Offset: 0x0f0 Description Control register for lane 1 Table 75. INTERP1_CTRL_LANE 1 Register Bits Name Description Type Reset 31:21 Reserved. - - - 20:19 FORCE_MSB ORed into bits 29:28 of the lane result presented to the RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x00 RW 0x00 RW 0x00 processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.
RP2040 Datasheet Table 77. INTERP1_ACCUM1_AD D Register Bits Description Type Reset 31:24 Reserved. - - 23:0 Values written here are atomically added to ACCUM1 RW 0x000000 Reading yields lane 1’s raw shift and mask value (BASE1 not added). SIO: INTERP1_BASE_1AND0 Register Offset: 0x0fc Table 78. INTERP1_BASE_1AND 0 Register Bits Description Type Reset 31:0 On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
RP2040 Datasheet level (level 0) is the highest priority. • Second, for interrupts with the same dynamic priority level, the lower-numbered IRQ has higher priority (using the IRQ numbers given in the table above). Some care has gone into arranging the RP2040 interrupt table to give a sensible default priority ordering, but individual interrupts can be raised or lowered in priority, using NVIC_IPR0 through NVIC_IPR7, to suit a particular use case.
RP2040 Datasheet The Instance IDs (top 4 bits of ID above) can be changed via a sysconfig register which may be useful in a multichip application. However note that ID=0xf is reserved for the internal Rescue DP (see Section 2.3.4.2). Figure 10. RP2040 sys_cfg.proc0_dap_instid Debugging Processors IO SWCLK SWD Multidrop arbiter SWD SWDIO SWD DAP_0 DP-0 AP SWD DAP_1 DP-1 AP Core0 Core1 SWD Rescue DP pam_restart sys_cfg.proc1_dap_instid 2.3.4.1.
RP2040 Datasheet • Power control optimization of system components. • Integrated sleep modes for low-power consumption. • Fast code execution enables running the processor with a slower clock or increasing sleep mode time. • Optimized code fetching for reduced flash and ROM power consumption. • Hardware multiplier. • Deterministic, high-performance interrupt handling for time-critical applications. • Deterministic instruction cycle timing. • Support for system level debug authentication.
RP2040 Datasheet 2.4.1.3. ARM architecture The processor implements the ARMv6-M architecture profile. See the ARMv6-M Architecture Reference Manual, and for further details refer to the ARM Cortex M0+ Technical Reference Manual. 2.4.2. Functional Description 2.4.2.1. Overview The Cortex-M0+ processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component.
RP2040 Datasheet • Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support. • Relocatable vector table. NOTE The NVIC supports hardware nesting of exceptions, e.g. an interrupt handler may itself be interrupted if a higherpriority interrupt request arrives whilst the handler is running. Further details available in Section 2.4.5. 2.4.2.4. Debug features Debug features are: • Four hardware breakpoints. • Two watchpoints.
RP2040 Datasheet NOTE Instructions are only fetched using the AHB-Lite interface. To optimize performance, the Cortex-M0+ processor fetches ahead of the instruction it is executing. To minimize power consumption, the fetch ahead is limited to a maximum of 32 bits. 2.4.2.7. Single-cycle I/O port The processor implements a single-cycle I/O port that provides high speed access to tightly-coupled peripherals, such as general-purpose-I/O (GPIO).
RP2040 Datasheet • rely on a mechanism that is transparent to software and provides low latency wakeup. The WFE mechanism relies on hardware and software working together to achieve energy saving. For example, stalling execution of a processor until a device or another processor has set a flag: • the hardware provides the mechanism to enter the WFE low-power state.
RP2040 Datasheet Note If PRIMASK.PM is set to 1, an asynchronous exception that has a higher group priority than any active exception results in a WFI instruction exit. If the group priority of the exception is less than or equal to the execution group priority, the exception is ignored. • If debug is enabled, a debug event. • A WFI wakeup event. The WFI instruction completes when the hardware detects a WFI wake up event. The processor recognizes WFI wake up events only after issuing the WFI instruction.
RP2040 Datasheet 2.4.3.2. Modes of operation and execution See the ARMv6-M Architecture Reference Manual for information about the modes of operation and execution. 2.4.3.3. Instruction set summary The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set comprises: • All of the 16-bit Thumb instructions from ARMv7-M excluding CBZ, CBNZ and IT.
RP2040 Datasheet Operation Description Assembler Cycles Bit clear BICS Rd, Rd, Rm 1 Move NOT MVNS Rd, Rm 1 AND test TST Rn, Rm 1 Logical shift left by immediate LSLS Rd, Rm, # 1 Logical shift left by register LSLS Rd, Rd, Rs 1 Logical shift right by immediate LSRS Rd, Rm, # 1 Logical shift right by register LSRS Rd, Rd, Rs 1 Arithmetic shift right ASRS Rd, Rm, # 1 Arithmetic shift right by register ASRS Rd, Rd, Rs 1 Rotate Rotate right by register RORS
RP2040 Datasheet Operation Extend Reverse State Hint Barriers Description Assembler Cycles With link BL
RP2040 Datasheet wait-state system, all debug accesses to system memory, NVIC, and debug resources are completely non-intrusive for typical code execution. The system memory map is ARMv6-M architecture compliant, and is common both to the debugger and processor accesses. Transactions are routed as follows: • All accesses below 0xd0000000 or above 0xefffffff appear as AHB-Lite transactions on the AHB-Lite master port of the processor.
RP2040 Datasheet Name Description PSR The Program Status Register (PSR) combines: • Application Program Status Register (APSR). • Interrupt Program Status Register (IPSR). • Execution Program Status Register (EPSR). These registers provide different views of the PSR. PRIMASK The PRIMASK register prevents activation of all exceptions with configurable priority. CONTROL The CONTROL register controls the stack used, the code privilege level, when the processor is in Thread mode.
RP2040 Datasheet 2.4.4.1. System control register summary Table 84 gives the system control registers. Each of these registers is 32 bits wide. Table 84.
RP2040 Datasheet NOTE "Nested" refers to the fact that interrupts can themselves be interrupted, by higher-priority interrupts. "Vectored" refers to the hardware dispatching each interrupt to a distinct handler routine, specified by the vector table. Details of nesting and vectoring behaviour are given in the ARMv6-M Architecture Reference Manual. All NVIC registers are only accessible using word transfers. Any attempt to read or write a halfword or byte individually is unpredictable.
RP2040 Datasheet 2.4.6. MPU 2.4.6.1. About the MPU The MPU is a component for memory protection which allows the processor to support the ARMv6 Protected Memory System Architecture model. The MPU provides full support for: • Eight unified protection regions. • Overlapping protection regions, with ascending region priority: ◦ 7 = highest priority. ◦ 0 = lowest priority. • Access permissions. • Exporting memory attributes to the system. MPU mismatches and permission violations invoke the HardFault handler.
RP2040 Datasheet 2.4.8. List of Registers The ARM Cortex-M0+ registers start at a base address of 0xe0000000 (defined as PPB_BASE in SDK). Table 87.
RP2040 Datasheet Description Use the SysTick Control and Status Register to enable the SysTick features. Table 88. SYST_CSR Register Bits Name Description Type Reset 31:17 Reserved. - - - 16 COUNTFLAG Returns 1 if timer counted to 0 since last time this was RO 0x0 - - read. Clears on read by application or debugger. 15:3 Reserved. - 2 CLKSOURCE SysTick clock source. Always reads as one if SYST_CALIB RW 0x0 reports NOREF.
RP2040 Datasheet Table 90. SYST_CVR Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:0 CURRENT Reads return the current value of the SysTick counter. This RW 0x000000 register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
RP2040 Datasheet Table 93. NVIC_ICER Register Bits Name Description Type Reset 31:0 CLRENA Interrupt clear-enable bits. RW 0x00000000 Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled. M0PLUS: NVIC_ISPR Register Offset: 0xe200 Description The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. Table 94. NVIC_ISPR Register Bits Name Description Type Reset 31:0 SETPEND Interrupt set-pending bits.
RP2040 Datasheet Table 96. NVIC_IPR0 Register Bits Name Description Type Reset 31:30 IP_3 Priority of interrupt 3 RW 0x0 29:24 Reserved. - - - 23:22 IP_2 Priority of interrupt 2 RW 0x0 21:16 Reserved. - - - 15:14 IP_1 Priority of interrupt 1 RW 0x0 13:8 Reserved. - - - 7:6 IP_0 Priority of interrupt 0 RW 0x0 5:0 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 7:6 IP_8 Priority of interrupt 8 RW 0x0 5:0 Reserved. - - - M0PLUS: NVIC_IPR3 Register Offset: 0xe40c Description Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Table 99. NVIC_IPR3 Register Bits Name Description Type Reset 31:30 IP_15 Priority of interrupt 15 RW 0x0 29:24 Reserved.
RP2040 Datasheet Description Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Table 101. NVIC_IPR5 Register Bits Name Description Type Reset 31:30 IP_23 Priority of interrupt 23 RW 0x0 29:24 Reserved. - - - 23:22 IP_22 Priority of interrupt 22 RW 0x0 21:16 Reserved. - - - 15:14 IP_21 Priority of interrupt 21 RW 0x0 13:8 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 15:14 IP_29 Priority of interrupt 29 RW 0x0 13:8 Reserved. - - - 7:6 IP_28 Priority of interrupt 28 RW 0x0 5:0 Reserved. - - - M0PLUS: CPUID Register Offset: 0xed00 Description Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. Table 104.
RP2040 Datasheet Bits Name Description Type Reset 31 NMIPENDSET Setting this bit will activate an NMI. Since NMI is the RW 0x0 highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending.
RP2040 Datasheet Bits Name Description Type Reset 23 ISRPREEMPT The system can only access this bit when the core is RO 0x0 halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. 22 ISRPENDING External interrupt pending flag RO 0x0 21 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 2 SYSRESETREQ Writing 1 to this bit causes the SYSRESETREQ signal to RW 0x0 RW 0x0 - - the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.
RP2040 Datasheet M0PLUS: CCR Register Offset: 0xed14 Description The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. Table 109. CCR Register Bits Name Description Type Reset 31:10 Reserved. - - - 9 STKALIGN Always reads as one, indicates 8-byte stack alignment on RO 0x0 - - exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment.
RP2040 Datasheet Description Use the System Handler Control and State Register to determine or clear the pending status of SVCall. Table 112. SHCSR Register Bits Name Description Type Reset 31:16 Reserved. - - - 15 SVCALLPENDED Reads as 1 if SVCall is Pending. Write 1 to set pending RW 0x0 - - SVCall, write 0 to clear pending SVCall. 14:0 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 1 HFNMIENA Controls the use of the MPU for HardFaults and NMIs. RW 0x0 RW 0x0 Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers. 0 ENABLE Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.
RP2040 Datasheet Bits Name Description Type Reset 4 VALID On writes, indicates whether the write must update the RW 0x0 RW 0x0 base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field.
RP2040 Datasheet Figure 12. DMA Architecture Overview. The read master can read data from some address every clock cycle. Likewise, the write master can write to another address. The address generator produces matched pairs of read and write addresses, which the masters consume through the address FIFOs. Up to 12 transfer sequences may be in progress The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle.
RP2040 Datasheet transfer. For example: • If the address does not increment (e.g. it is the address of a peripheral FIFO), and the next transfer sequence is to/from that same address, there is no need to write to the register again. • When transferring to/from a consecutive series of buffers in memory (e.g. scattering and gathering), an address register will already have incremented to the start of the next buffer at the completion of a transfer.
RP2040 Datasheet 2.5.2. Starting Channels There are three ways to start a channel: • Writing to a channel trigger register • A chain trigger from another channel which has just completed, and has its CHAIN_TO field configured • The MULTI_CHAN_TRIGGER register, which can start multiple channels at once Each of these covers different use cases.
RP2040 Datasheet • The value 0 is written to the trigger register. (This is useful for ending control block chains. See null triggers, Section 2.5.2.3) 2.5.2.2. Chaining When a channel completes, it can name a different channel to immediately be triggered. This can be used as a callback for the second channel to reconfigure and restart the first. This feature is configured through the CHAIN_TO field in the channel CTRL register. This 4-bit value selects a channel that will start when this one finishes.
RP2040 Datasheet 2.5.3.1. System DREQ Table There is a global assignment of DREQ numbers to peripheral DREQ channels. Table 119.
RP2040 Datasheet channel and peripheral to become desynchronised, and can cause corruption or loss of data. Another caveat is that multiple channels should not be connected to the same DREQ. 2.5.4. Interrupts Each channel can generate interrupts; these can be masked on a per-channel basis using the INTE0 or INTE1 registers. There are two circumstances where a channel raises an interrupt request: • On the completion of each transfer sequence, if CTRL.
RP2040 Datasheet • Bit reversal • Byte swap These manipulations do not affect the CRC calculation, just how the data is presented in the result register. 2.5.5.3. Channel Abort It is possible for a channel to get into an irrecoverable state: e.g. if commanded to transfer more data than a peripheral will ever request, it will never complete. Clearing the CTRL.EN bit merely pauses the channel, and does not solve the problem.
RP2040 Datasheet NOTE Having two system interrupt lines allows different channel completion interrupts to be routed to different cores, or to preempt one another on the same core if one channel is more time-critical. When the interrupt is asserted, the processor can be configured to drop whatever it is doing and call a user-specified handler function. The handler can reconfigure and restart the channel. When the handler exits, the processor returns to the interrupted code running in the foreground.
RP2040 Datasheet 79 // Tell the DMA to raise IRQ line 0 when the channel finishes a block 80 dma_channel_set_irq0_enabled(dma_chan, true); 81 82 // Configure the processor to run dma_handler() when DMA IRQ 0 is asserted 83 irq_set_exclusive_handler(DMA_IRQ_0, dma_handler); 84 irq_set_enabled(DMA_IRQ_0, true); 85 86 // Manually call the handler once, to trigger the first transfer 87 dma_handler(); 88 89 // Everything else from this point is interrupt-driven.
RP2040 Datasheet 16 // These buffers will be DMA'd to the UART, one after the other. 17 18 const char word0[] = "Transferring "; 19 const char word1[] = "one "; 20 const char word2[] = "word "; 21 const char word3[] = "at "; 22 const char word4[] = "a "; 23 const char word5[] = "time.\n"; 24 25 // Note the order of the fields here: it's important that the length is before 26 // the read address, because the control channel is going to write to the last 27 // two registers in alias 3 on the data channel: 28
RP2040 Datasheet 79 80 // The data channel is set up to write to the UART FIFO (paced by the 81 // UART's TX data request signal) and then chain to the control channel 82 // once it completes. The control channel programs a new read address and 83 // data length, and retriggers the data channel.
RP2040 Datasheet Offset Name Info 0x020 CH0_AL2_CTRL Alias for channel 0 CTRL register 0x024 CH0_AL2_TRANS_COUNT Alias for channel 0 TRANS_COUNT register 0x028 CH0_AL2_READ_ADDR Alias for channel 0 READ_ADDR register 0x02c CH0_AL2_WRITE_ADDR_TRIG Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
RP2040 Datasheet Offset Name Info 0x094 CH2_AL1_READ_ADDR Alias for channel 2 READ_ADDR register 0x098 CH2_AL1_WRITE_ADDR Alias for channel 2 WRITE_ADDR register 0x09c CH2_AL1_TRANS_COUNT_TRIG Alias for channel 2 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
RP2040 Datasheet Offset Name Info 0x104 CH4_WRITE_ADDR DMA Channel 4 Write Address pointer 0x108 CH4_TRANS_COUNT DMA Channel 4 Transfer Count 0x10c CH4_CTRL_TRIG DMA Channel 4 Control and Status 0x110 CH4_AL1_CTRL Alias for channel 4 CTRL register 0x114 CH4_AL1_READ_ADDR Alias for channel 4 READ_ADDR register 0x118 CH4_AL1_WRITE_ADDR Alias for channel 4 WRITE_ADDR register 0x11c CH4_AL1_TRANS_COUNT_TRIG Alias for channel 4 TRANS_COUNT register This is a trigger register (0xc).
RP2040 Datasheet Offset Name Info 0x178 CH5_AL3_TRANS_COUNT Alias for channel 5 TRANS_COUNT register 0x17c CH5_AL3_READ_ADDR_TRIG Alias for channel 5 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
RP2040 Datasheet Offset Name Info 0x1ec CH7_AL2_WRITE_ADDR_TRIG Alias for channel 7 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
RP2040 Datasheet Offset Name Info 0x25c CH9_AL1_TRANS_COUNT_TRIG Alias for channel 9 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
RP2040 Datasheet Offset Name Info 0x2cc CH11_CTRL_TRIG DMA Channel 11 Control and Status 0x2d0 CH11_AL1_CTRL Alias for channel 11 CTRL register 0x2d4 CH11_AL1_READ_ADDR Alias for channel 11 READ_ADDR register 0x2d8 CH11_AL1_WRITE_ADDR Alias for channel 11 WRITE_ADDR register 0x2dc CH11_AL1_TRANS_COUNT_TRIG Alias for channel 11 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
RP2040 Datasheet Offset Name Info 0x42c TIMER3 Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
RP2040 Datasheet Offset Name Info 0x940 CH5_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x944 CH5_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x980 CH6_DBG_CTDREQ Read: get channel DREQ counter (i.e.
RP2040 Datasheet Description DMA Channel N Read Address pointer Table 121. CH0_READ_ADDR, CH1_READ_ADDR, …, CH10_READ_ADDR, Bits Description Type Reset 31:0 This register updates automatically each time a read completes. The current RW 0x00000000 value is the next address to be read by this channel.
RP2040 Datasheet Bits Name Description Type Reset 31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. RO 0x0 WC 0x0 WC 0x0 - - The channel halts when it encounters any bus error, and always raises its channel IRQ flag. 30 READ_ERROR If 1, the channel received a read bus error. Write one to clear.
RP2040 Datasheet Bits Name Description Type Reset 20:15 TREQ_SEL Select a Transfer Request signal. RW 0x00 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
RP2040 Datasheet Bits Name Description Type Reset 1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in RW 0x0 RW 0x0 issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed.
RP2040 Datasheet Table 128. CH0_AL1_TRANS_COU NT_TRIG, CH1_AL1_TRANS_COU Bits Description Type Reset 31:0 Alias for channel N TRANS_COUNT register RO - NT_TRIG, …, This is a trigger register (0xc). Writing a nonzero value will CH10_AL1_TRANS_CO reload the channel counter and start the channel. UNT_TRIG, CH11_AL1_TRANS_CO UNT_TRIG Registers DMA: CH0_AL2_CTRL, CH1_AL2_CTRL, …, CH10_AL2_CTRL, CH11_AL2_CTRL Registers Offsets: 0x020, 0x060, …, 0x2a0, 0x2e0 Table 129.
RP2040 Datasheet Table 134. CH0_AL3_WRITE_ADD R, CH1_AL3_WRITE_ADD Bits Description Type Reset 31:0 Alias for channel N WRITE_ADDR register RO - R, …, CH10_AL3_WRITE_AD DR, CH11_AL3_WRITE_AD DR Registers DMA: CH0_AL3_TRANS_COUNT, CH1_AL3_TRANS_COUNT, CH10_AL3_TRANS_COUNT, CH11_AL3_TRANS_COUNT Registers …, Offsets: 0x038, 0x078, …, 0x2b8, 0x2f8 Table 135.
RP2040 Datasheet Bits Name Description Type Reset 23 SNIFF_EN If 1, this channel’s data transfers are visible to the sniff RW 0x0 RW 0x0 In QUIET mode, the channel does not generate IRQs at the RW 0x0 hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a percontrol- block basis. 22 BSWAP Apply byte-swap transformation to DMA data.
RP2040 Datasheet Bits Name Description Type Reset 5 INCR_WRITE If 1, the write address increments with each transfer. If 0, RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. 4 INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.
RP2040 Datasheet Bits Name Description Type Reset 29 WRITE_ERROR If 1, the channel received a write bus error. Write one to WC 0x0 - - clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) 28:25 Reserved. - 24 BUSY This flag goes high when the channel starts a new transfer RO 0x0 sequence, and low when the last transfer of that sequence completes.
RP2040 Datasheet Bits Name Description Type Reset 10 RING_SEL Select whether RING_SIZE applies to read or write RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. 9:6 RING_SIZE Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change.
RP2040 Datasheet Description DMA Channel 3 Control and Status Table 139. CH3_CTRL_TRIG Register Bits Name Description Type Reset 31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. RO 0x0 WC 0x0 WC 0x0 - - The channel halts when it encounters any bus error, and always raises its channel IRQ flag. 30 READ_ERROR If 1, the channel received a read bus error. Write one to clear.
RP2040 Datasheet Bits Name Description Type Reset 20:15 TREQ_SEL Select a Transfer Request signal. RW 0x00 RW 0x3 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
RP2040 Datasheet Bits Name Description Type Reset 1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in RW 0x0 RW 0x0 issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed.
RP2040 Datasheet Bits Name Description Type Reset 23 SNIFF_EN If 1, this channel’s data transfers are visible to the sniff RW 0x0 RW 0x0 In QUIET mode, the channel does not generate IRQs at the RW 0x0 hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a percontrol- block basis. 22 BSWAP Apply byte-swap transformation to DMA data.
RP2040 Datasheet Bits Name Description Type Reset 5 INCR_WRITE If 1, the write address increments with each transfer. If 0, RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. 4 INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.
RP2040 Datasheet Bits Name Description Type Reset 29 WRITE_ERROR If 1, the channel received a write bus error. Write one to WC 0x0 - - clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) 28:25 Reserved. - 24 BUSY This flag goes high when the channel starts a new transfer RO 0x0 sequence, and low when the last transfer of that sequence completes.
RP2040 Datasheet Bits Name Description Type Reset 10 RING_SEL Select whether RING_SIZE applies to read or write RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. 9:6 RING_SIZE Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change.
RP2040 Datasheet Description DMA Channel 6 Control and Status Table 142. CH6_CTRL_TRIG Register Bits Name Description Type Reset 31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. RO 0x0 WC 0x0 WC 0x0 - - The channel halts when it encounters any bus error, and always raises its channel IRQ flag. 30 READ_ERROR If 1, the channel received a read bus error. Write one to clear.
RP2040 Datasheet Bits Name Description Type Reset 20:15 TREQ_SEL Select a Transfer Request signal. RW 0x00 RW 0x6 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
RP2040 Datasheet Bits Name Description Type Reset 1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in RW 0x0 RW 0x0 issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed.
RP2040 Datasheet Bits Name Description Type Reset 23 SNIFF_EN If 1, this channel’s data transfers are visible to the sniff RW 0x0 RW 0x0 In QUIET mode, the channel does not generate IRQs at the RW 0x0 hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a percontrol- block basis. 22 BSWAP Apply byte-swap transformation to DMA data.
RP2040 Datasheet Bits Name Description Type Reset 5 INCR_WRITE If 1, the write address increments with each transfer. If 0, RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. 4 INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.
RP2040 Datasheet Bits Name Description Type Reset 29 WRITE_ERROR If 1, the channel received a write bus error. Write one to WC 0x0 - - clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) 28:25 Reserved. - 24 BUSY This flag goes high when the channel starts a new transfer RO 0x0 sequence, and low when the last transfer of that sequence completes.
RP2040 Datasheet Bits Name Description Type Reset 10 RING_SEL Select whether RING_SIZE applies to read or write RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. 9:6 RING_SIZE Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change.
RP2040 Datasheet Description DMA Channel 9 Control and Status Table 145. CH9_CTRL_TRIG Register Bits Name Description Type Reset 31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. RO 0x0 WC 0x0 WC 0x0 - - The channel halts when it encounters any bus error, and always raises its channel IRQ flag. 30 READ_ERROR If 1, the channel received a read bus error. Write one to clear.
RP2040 Datasheet Bits Name Description Type Reset 20:15 TREQ_SEL Select a Transfer Request signal. RW 0x00 RW 0x9 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
RP2040 Datasheet Bits Name Description Type Reset 1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in RW 0x0 RW 0x0 issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed.
RP2040 Datasheet Bits Name Description Type Reset 23 SNIFF_EN If 1, this channel’s data transfers are visible to the sniff RW 0x0 RW 0x0 In QUIET mode, the channel does not generate IRQs at the RW 0x0 hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a percontrol- block basis. 22 BSWAP Apply byte-swap transformation to DMA data.
RP2040 Datasheet Bits Name Description Type Reset 5 INCR_WRITE If 1, the write address increments with each transfer. If 0, RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. 4 INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.
RP2040 Datasheet Bits Name Description Type Reset 29 WRITE_ERROR If 1, the channel received a write bus error. Write one to WC 0x0 - - clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) 28:25 Reserved. - 24 BUSY This flag goes high when the channel starts a new transfer RO 0x0 sequence, and low when the last transfer of that sequence completes.
RP2040 Datasheet Bits Name Description Type Reset 10 RING_SEL Select whether RING_SIZE applies to read or write RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. 9:6 RING_SIZE Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change.
RP2040 Datasheet Description Interrupt Status (raw) Table 148. INTR Register Bits Description Type Reset 31:16 Reserved. - - 15:0 Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. RO 0x0000 Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.
RP2040 Datasheet Table 151. INTS0 Register Bits Description Type Reset 31:16 Reserved. - - 15:0 Indicates active channel interrupt requests which are currently causing IRQ 0 WC 0x0000 to be asserted. Channel interrupts can be cleared by writing a bit mask here. DMA: INTE1 Register Offset: 0x414 Description Interrupt Enables for IRQ 1 Table 152. INTE1 Register Bits Description Type Reset 31:16 Reserved. - - 15:0 Set bit n to pass interrupts from channel n to DMA IRQ 1.
RP2040 Datasheet Table 155. TIMER0, TIMER1, TIMER2, TIMER3 Registers Bits Name Description Type Reset 31:16 X Pacing Timer Dividend. Specifies the X value for the (X/Y) RW 0x0000 RW 0x0000 fractional timer. 15:0 Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. DMA: MULTI_CHAN_TRIGGER Register Offset: 0x430 Description Trigger one or more channels simultaneously Table 156. MULTI_CHAN_TRIGGE R Register Bits Description Type Reset 31:16 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 8:5 CALC 0x0 → Calculate a CRC-32 (IEEE802.3 polynomial) RW 0x0 0x1 → Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data 0x2 → Calculate a CRC-16-CCITT 0x3 → Calculate a CRC-16-CCITT with bit reversed data 0xe → XOR reduction over all data. == 1 if the total 1 population count is odd.
RP2040 Datasheet Table 160. CHAN_ABORT Register Bits Description Type Reset 31:16 Reserved. - - 15:0 Each bit corresponds to a channel. Writing a 1 aborts whatever transfer SC 0x0000 sequence is in progress on that channel. The bit will remain high until any inflight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.
RP2040 Datasheet • Flash boot sequence • Flash programming routines • USB mass storage device with UF2 support • Utility libraries such as fast floating point The boot sequence of the chip is defined in Section 2.8.1, and the ROM contents is described in more detail in Section 2.8. The full source code for the RP2040 bootrom is available at: https://github.
RP2040 Datasheet the processors never stall on these accesses. However, like all SRAM on RP2040, these banks have single-cycle access from all masters providing no other masters are accessing the bank in the same cycle, so it is reasonable to treat memory as a single 264kB device. The four 64kB banks are also available at a non-striped mirror. The four 64kB regions starting at 0x21000000, 0x21010000, 0x21020000, 0x21030000 are each mapped directly to one of the four 64kB SRAM banks.
RP2040 Datasheet Figure 14. Flash execute-in-place (XIP) subsystem. System accesses via the main AHB-Lite slave are decoded to determine if they are XIP accesses, direct accesses to the SSI e.g. for configuration, or accesses to various other hardware and control registers in the XIP subsystem. XIP accesses are first looked up in the cache, to accelerate accesses to recentlyused data.
RP2040 Datasheet 2.6.3.2. Cache Flushing and Maintenance The FLUSH register allows the entire cache contents to be flushed. This is necessary if software has reprogrammed the flash contents, and needs to clear out stale data and code, without performing a reboot. Cache flushes are triggered either manually by writing 1 to FLUSH, or automatically when the XIP block is brought out of reset.
RP2040 Datasheet XIP access. This includes the possibility of issuing a standard 03h serial flash read command for each access, allowing virtually any serial flash device to be used. The maximum SPI clock frequency is half the system clock frequency. The SSI can also be used as a standard FIFO-based SPI master, with DMA support. This mode is used by the bootrom to extract the second stage bootloader from external flash (see Section 2.8.1).
RP2040 Datasheet 2.6.3.5. Performance Counters The XIP subsystem provides two performance counters. These are 32 bits in size, saturate upon reaching 0xffffffff, and are cleared by writing any value. They count: 1. The total number of XIP accesses, to any alias 2. The number of XIP accesses which resulted in a cache hit For common use cases, this allows the cache hit rate to be profiled. 2.6.3.6.
RP2040 Datasheet Bits Name Description Type Reset 0 EN When 1, enable the cache. When the cache is disabled, all RW 0x1 XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response.
RP2040 Datasheet Description Cache Hit counter Table 169. CTR_HIT Register Bits Description Type Reset 31:0 A 32 bit saturating counter that increments upon each cache hit, WC 0x00000000 i.e. when an XIP access is serviced directly from cached data. Write any value to clear. XIP: CTR_ACC Register Offset: 0x10 Description Cache Access counter Table 170.
RP2040 Datasheet Table 172. STREAM_CTR Register Bits Description Type Reset 31:22 Reserved. - - 21:0 Write a nonzero value to start a streaming read. This will then RW 0x000000 progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0.
RP2040 Datasheet • USB PICOBOOT bootloader interface for advanced management. • Routines for programming and manipulating the external flash. • Fast floating point library. • Fast bit counting / manipulation functions. • Fast memory fill / copy functions. Bootrom Source Code The full source for the RP2040 bootrom can be found at https://github.com/raspberrypi/pico-bootrom. This includes both version 1 and version 2 of the bootrom, which correspond to the B0 and B1 silicon revisions, respectively. 2.8.1.
RP2040 Datasheet ◦ The debug host (which initiated the rescue) will provide further instruction. • If watchdog scratch registers set to indicate pre-loaded code exists in SRAM, jump to that code • Check if SPI CS pin is tied low ("bootrom button"), and skip flash boot if so.
RP2040 Datasheet After issuing the XIP exit sequence, the Bootrom attempts to read in the second stage from flash using standard 03h serial read commands, which are near-universally supported. Since the Bootrom is immutable, it aims for compatibility rather than performance. 2.8.1.3. Flash Second Stage The flash second stage must configure the SSI and the external flash for the best possible execute-in-place performance.
RP2040 Datasheet 0x00000016 16-bit pointer Pointer to a public data lookup table (rom_data_table) 0x00000018 16-bit pointer Pointer to a helper function (rom_table_lookup()) 2.8.2.1. Bootrom Functions The Bootrom contains a number of public functions that provide useful RP2040 functionality that might be needed in the absence of any other code on the device, as well as highly optimized versions of certain key functionality that would otherwise have to take up space in most user binaries.
RP2040 Datasheet Table 175. Fast Bit Counting / CODE Manipulation Functions. 'P','3' Cycles Avg Cycles Avg Description V1 V2 18 20 uint32_t _popcount32(uint32_t value) Return a count of the number of 1 bits in value. 'R','3' 21 22 uint32_t _reverse32(uint32_t value) Return the bits of value in the reverse order. 'L','3' 13 9.6 uint32_t _clz32(uint32_t value) Return the number of consecutive high order 0 bits of value. If value is zero, returns 32.
RP2040 Datasheet 'E','X' void _flash_exit_xip(void) First set up the SSI for serial-mode operations, then issue the fixed XIP exit sequence described in Section 2.8.1.2. Note that the bootrom code uses the IO forcing logic to drive the CS pin, which must be cleared before returning the SSI to XIP mode (e.g. by a call to _flash_flush_cache). This function configures the SSI with a fixed SCK clock divisor of /6.
RP2040 Datasheet 'D','E' _debug_trampoline_end This is the address of the final BKPT #0 instruction of debug_trampoline. This can be compared with the program counter to detect completion of the debug_trampoline call. 2.8.2.1.5. Miscellaneous Functions These remaining functions don’t fit in other categories and are exposed in the SDK via the pico_bootrom library (see pico_bootrom). Table 179.
RP2040 Datasheet The scientific functions always return results within 1 ULP (unit in last place) of the exact result. In many cases results are better. The scientific functions are calculated using internal fixed-point representations so accuracy (as measured in ULP error rather than in absolute terms) is poorer in situations where converting the result back to floating point entails a large normalising shift.
RP2040 Datasheet 0x10 N/A N/A deprecated Do not use this function 0x14 N/A N/A deprecated Do not use this function 0x18 63 63 float _fsqrt(float v) Return 0x1c 37 40 or -Infinity if v is negative.
RP2040 Datasheet 0x40 593 577 float _fsin(float angle) Return the sine of angle. angle is in radians, and must be in the range -128 to 128 0x44 669 653 float _ftan(float angle) Return the tangent of angle. angle is in radians, and must be in the range -128 to 128 0x48 N/A N/A deprecated Do not use this function 0x4c 542 524 float _fexp(float v) Return the exponential value of v, i.e. so 0x50 810 789 float _fln( float v) Return the natural logarithm of v.
RP2040 Datasheet 0x70 N/A 53 _float2fix64 Convert a float to a signed fixed point 64-bit integer representation where n specifies the position of the binary point in the resulting fixed point representation - e.g. _float2fix(0.5f, 16) == 0x8000.
RP2040 Datasheet Offset V2 Cycles Description (Avg) 0x20 74 int _double2fix(double v, int n) Convert a double to a signed fixed point integer representation where n specifies the position of the binary point in the resulting fixed point representation - e.g. _double2fix(0.5f, 16) == 0x8000.
RP2040 Datasheet Offset V2 Cycles Description (Avg) 0x50 428 double _dln( double v) Return the natural logarithm of v.
RP2040 Datasheet Offset V2 Cycles Description (Avg) 0x78 52 _double2ufix64 Convert a double to an unsigned fixed point 64-bit integer representation where n specifies the position of the binary point in the resulting fixed point representation, e.g. _double2ufix(0.5f, 16) == 0x8000. This method rounds towards -Infinity, and clamps the resulting integer to lie within the range 0x0000000000000000 to 0xFFFFFFFFFFFFFFFF 0x7c 23 float _double2float(double v) Converts a double to a float 2.8.2.3.
RP2040 Datasheet 2.8.3.1. The RPI-RP2 Drive The RP2040 appears as a standard 128MB flash drive named RPI-RP2 formatted as a single partition with FAT16. There are only ever two actual files visible on the drive specified. • INFO_UF2.TXT - contains a string description of the UF2 bootloader and version. • INDEX.HTM - redirects to information about the RP2040 device.
RP2040 Datasheet Note that after downloading a regular flash binary, a reset is performed after which the flash binary second stage (at address 0x10000000 - the start of flash) will be entered (if valid) via the bootrom. A downloaded RAM Only binary is entered by watchdog reset into the start of the binary, which is calculated as the lowest address of a downloaded block (with Main RAM considered lower than Flash Cache if both are present).
RP2040 Datasheet Table 184. PICOBOOT Interface Descriptor Field Value bLength 9 bDescriptorType 4 bInterfaceNumber varies bAlternateSetting 0 bNumEndpoints 2 bInterfaceClass 0xff (vendor specific) bInterfaceSubClass 0 bInterfaceProtocol 0 iInterface 0 2.8.4.3. Identifying The Endpoints The PICOBOOT interface provides a single BULK OUT and a single BULK IN endpoint. These can be identified by their direction and type. You should not rely on endpoint numbers. 2.8.4.4.
RP2040 Datasheet Table 186.
RP2040 Datasheet 2.8.4.4.4. READ (0x84) Read a contiguous memory (Flash or RAM or ROM) range from the RP2040 Table 189. PICOBOOT Read memory command (Flash, RAM, ROM) structure Offset Name Value / Description 0x08 bCmdId 0x84 (READ) 0x09 bCmdSize 0x08 0x0c dTransferLength Must be the same as dSize 0x10 dAddr The address to read from. May be in Flash or RAM or ROM 0x14 dSize The number of bytes to read 2.8.4.4.5.
RP2040 Datasheet Offset Name Value / Description 0x09 bCmdSize 0x00 0x0c dTransferLength 0x00000000 2.8.4.4.8. EXEC (0x08) Executes a function on the device. This function takes no arguments and returns no results, so it must communicate via RAM. Execution of this method will block any other commands as well as Mass Storage Interface UF2 writes, so should only be used in exclusive mode and with extreme care (and it should save and restore registers as per the ARM EABI).
RP2040 Datasheet 2.8.4.5. Control Requests The following requests are sent to the interface via the default control pipe. 2.8.4.5.1. INTERFACE_RESET (0x41) The host sends this control request to reset the PICOBOOT interface. This command: • Clears the HALT condition (if set) on each of the bulk endpoints • Aborts any in-process PICOBOOT or Mass Storage transfer and any flash write (this method is the only way to kill a stuck flash transfer).
RP2040 Datasheet Offset Name Description 0x04 dStatusCode OK (0) The command completed successfully (or is in still in progress) UNKNOWN_CMD (1) The ID of the command was not recognized INVALID_CMD_LENGTH (2) The length of the command request was incorrect INVALID_TRANSFER_LENG The data transfer length was incorrect given the TH (3) command INVALID_ADDRESS (4) The address specified was invalid for the command type; i.e.
RP2040 Datasheet CAUTION If the digital IO is powered at a nominal 1.8V, the IO input thresholds should be adjusted via the VOLTAGE_SELECT register. By default, the IO input thresholds are valid when the digital IO is powered at a nominal voltage between 2.5V and 3.3V. See Section 2.19, “GPIO” for details. Powering the IO at 1.8V with input thresholds set for a 2.5V to 3.3V supply is a safe operating mode, but will result in input thresholds that do not meet specification.
RP2040 Datasheet NOTE It is safe to supply ADC_AVDD at a higher or lower voltage than IOVDD, e.g. to power the ADC at 3.3V, for optimum performance, while supporting 1.8V signal levels on the digital IO. But the voltage on the ADC analogue inputs must not exceed IOVDD, e.g. if IOVDD is powered at 1.8V, the voltage on the ADC inputs should be limited to 1.8V. Voltages greater than IOVDD will result in leakage currents through the ESD protection diodes. See Section 5.2.3, “Pin Specifications” for details.
RP2040 Datasheet 2.9.7.2. External Core Supply The digital core (DVDD) can be powered directly from an external 1.1V supply, rather than from the on-chip regulator, as shown in Figure 17. This approach may make sense if a suitable external regulator is available elsewhere in the system, or for low power applications where an efficient switched-mode regulator could be used instead of the less efficient linear on-chip voltage regulator.
RP2040 Datasheet Figure 18. supporting 1.8V IO while using USB and the ADC 2.9.7.4. Single 1.8V Supply If a functional USB PHY and optimum ADC performance are not required, RP2040 can be powered from a single supply of less than 3.3V. Figure 19 shows an example with a single 1.8V supply. In this example, the core supply (DVDD) is regulated from the 1.8V supply by the on-chip voltage regulator. Figure 19. powering the chip from a single 1.8V supply 2.10.
RP2040 Datasheet with the chip’s digital IO supply IOVDD, simplifying the overall power supply requirements. To allow the chip to start up, the voltage regulator is enabled by default and will power-on as soon as its input supply is available. Once the chip is out of reset, the regulator can be disabled, placed into a high impedance state, or have its output voltage adjusted, under software control. The output voltage can be set in the range 0.80V to 1.30V in 50mV steps, but is set to a nominal 1.
RP2040 Datasheet 2.10.2.2. High Impedance Mode In High Impedance mode, the voltage regulator is disabled and its output pin (VREG_VOUT) is set to a high impedance state. In this mode, the regulator’s power consumption is minimised. This mode allows a load connected to VREG_VOUT to be powered from a power source other than the on-chip regulator.
RP2040 Datasheet in SDK). Table 199. List of VREG_AND_CHIP_RES ET registers Offset Name Info 0x0 VREG Voltage regulator control and status 0x4 BOD brown-out detection control 0x8 CHIP_RESET Chip reset control and status VREG_AND_CHIP_RESET: VREG Register Offset: 0x0 Description Voltage regulator control and status Table 200. VREG Register Bits Name Description Type Reset 31:13 Reserved. - - - 12 ROK regulation status RO 0x0 0=not in regulation, 1=in regulation 11:8 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 7:4 VSEL threshold select RW 0x9 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V 3:1 Reserved. - - - 0 EN enable RW 0x1 0=not enabled, 1=enabled VREG_AND_CHIP_RESET: CHIP_RESET Register Offset: 0x8 Description Chip reset control and status Table 202.
RP2040 Datasheet 2.10.7. Detailed Specifications Table 203. Voltage Parameter Regulator Detailed Specifications VVREG_VIN Description Min Typ Max Units input supply 1.63 1.8 - 3.3 3.63 V voltage ΔVVREG_VOUT output voltage -3 +3 variation IMAX output current ILIMIT current limit 150 ROKTH.
RP2040 Datasheet 2.11.2. SLEEP State RP2040 enters the SLEEP state when all of the following are true: • Both processors are asleep (e.g. in a WFE or WFI instruction) • The system DMA has no outstanding transfers on any channel RP2040 exits the SLEEP state when either processor is awoken by an interrupt. When in the SLEEP state, the top-level clock gates are masked by the SLEEP_ENx registers (starting at SLEEP_EN0), rather than the WAKE_ENx registers.
RP2040 Datasheet CAUTION Memories must not be accessed when powered down. Doing so can corrupt memory contents. When powering a memory back up, a 20 ns delay is required before accessing the memory again. The XIP cache (see Section 2.6.3) can also be powered down, with CTRL.POWER_DOWN. The XIP hardware will not generate cache accesses whilst the cache is powered down.
RP2040 Datasheet 2.11.5.2. Dormant The hello_dormant example, https://github.com/raspberrypi/pico-playground/tree/master/sleep/hello_dormant/ hello_dormant.c, demonstrates dormant mode.
RP2040 Datasheet Figure 21. The chiplevel reset subsystem 2.12.2. Power-on Reset The power-on reset block makes sure the chip starts up cleanly when power is first applied by holding it in reset until the digital core supply (DVDD) can reliably power the chip’s core logic. The block holds its por_n output low until DVDD has been above the power-on reset threshold (DVDDTH.POR) for a period greater than the power-on reset assertion delay (tPOR.ASSERT).
RP2040 Datasheet Table 204. Power-on Reset Parameters Parameter Description Min Typ Max Units DVDDTH.POR power-on reset 0.924 0.957 0.99 V 3 10 μs threshold tPOR.ASSERT power-on reset assertion delay 2.12.3. Brown-out Detection The brown-out detection block prevents unreliable operation by initiating a power-on reset cycle if the digital core supply (DVDD) drops below a safe operating level.
RP2040 Datasheet Figure 25. Disabling and enabling brownout detection EN 1 0 1 tBOD.ENABLE detection inactive detection inactive detection active Detection is re-enabled if the BOD register is reset, as this sets the register’s EN field to one. Again, detection will become active after a delay equal to the brown-out detection enable delay (tBOD.ENABLE).
RP2040 Datasheet Parameter Description tBOD.ASSERT brown-out Min Typ Max Units 3 10 μs 35 55 μs 20 30 μs detection assertion delay tBOD.ENABLE brown-out detection enable delay tBOD.PROG brown-out detection programming delay 2.12.4. Supply Monitor The power-on and brown-out reset blocks are powered by the on-chip voltage regulator’s input supply (VREG_VIN).
RP2040 Datasheet and a one in the HAD_PSM_RESTART field indicates the chip has been reset via Rescue Debug Port. There should never be more than one field set to one. 2.12.8. List of Registers The chip-level reset subsystem shares a register address space with the on-chip voltage regulator. The registers for both subsystems are listed in Section 2.10.6. The shared address space is referred to as vreg_and_chip_reset elsewhere in this document. 2.13. Power-On State Machine 2.13.1.
RP2040 Datasheet • Crystal Oscillator reset is deasserted. The crystal oscillator is not started at this point, so rst_done is asserted instantly. • clk_ref and clk_sys clock generators are taken out of reset. In the initial configuration clk_ref is running from the ring oscillator with no divider. clk_sys is running from clk_ref. These clocks are needed for the rest of the sequence to progress.
RP2040 Datasheet PSM: FRCE_ON Register Offset: 0x0 Description Force block out of reset (i.e. power it on) Table 208. FRCE_ON Register Bits Name Description Type Reset 31:17 Reserved.
RP2040 Datasheet Bits Name 9 Description Type Reset SRAM3 RW 0x0 8 SRAM2 RW 0x0 7 SRAM1 RW 0x0 6 SRAM0 RW 0x0 5 ROM RW 0x0 4 BUSFABRIC RW 0x0 3 RESETS RW 0x0 2 CLOCKS RW 0x0 1 XOSC RW 0x0 0 ROSC RW 0x0 PSM: WDSEL Register Offset: 0x8 Description Set to 1 if this peripheral should be reset when the watchdog fires. Table 210. WDSEL Register Bits Name Description Type Reset 31:17 Reserved.
RP2040 Datasheet Description Indicates the peripheral’s registers are ready to access. Table 211. DONE Register Bits Name Description Type Reset 31:17 Reserved.
RP2040 Datasheet 2.14.2. Programmer’s Model The SDK defines a struct to represent the resets registers. SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2040/hardware_structs/include/hardware/structs/resets.h Lines 13 - 19 13 typedef struct { 14 io_rw_32 reset; 15 io_rw_32 wdsel; 16 io_rw_32 reset_done; 17 } resets_hw_t; 18 19 #define resets_hw ((resets_hw_t *const)RESETS_BASE) Three registers are defined: • reset: this register contains a bit for each peripheral that can be reset.
RP2040 Datasheet 32 static inline void uart_unreset(uart_inst_t *uart) { 33 invalid_params_if(UART, uart != uart0 && uart != uart1); 34 unreset_block_wait(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS); 35 } 2.14.3. List of Registers The reset controller registers start at a base address of 0x4000c000 (defined as RESETS_BASE in SDK). Table 212. List of RESETS registers Offset Name Info 0x0 RESET Reset control. 0x4 WDSEL Watchdog select. 0x8 RESET_DONE Reset done.
RP2040 Datasheet Bits Name 5 Description Type Reset IO_BANK0 RW 0x1 4 I2C1 RW 0x1 3 I2C0 RW 0x1 2 DMA RW 0x1 1 BUSCTRL RW 0x1 0 ADC RW 0x1 RESETS: WDSEL Register Offset: 0x4 Description Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. Table 214. WDSEL Register Bits Name Description Type Reset 31:25 Reserved.
RP2040 Datasheet Bits Name 1 0 Description Type Reset BUSCTRL RW 0x0 ADC RW 0x0 RESETS: RESET_DONE Register Offset: 0x8 Description Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral’s registers are ready to be accessed. Table 215. RESET_DONE Register Bits Name Description Type Reset 31:25 Reserved.
RP2040 Datasheet 2.15. Clocks 2.15.1. Overview The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock sources allowing the user to trade off performance against cost, board area and power consumption. From these sources it uses multiple clock generators to provide the required clocks.
RP2040 Datasheet 2.15.2. Clock sources The RP2040 can be run from a variety of clock sources. This flexibility allows the user to optimise the clock setup for performance, cost, board area and power consumption. The sources include the on-chip Ring Oscillator (Section 2.17), the Crystal Oscillator (Section 2.16), external clocks from GPIOs (Section 2.15.6.4) and the PLLs (Section 2.18). The list of clock sources is different per clock generator and can be found as enumerated values in the CTRL register.
RP2040 Datasheet 2.15.2.1.2. Mitigating ROSC frequency variation due to voltage Supply voltage varies for two reasons. Firstly, the power supply itself may vary, and secondly, there will be varying onchip IR drop as chip activity varies. If the application has a minimum performance target then the user needs to calibrate for that application and adjust the ROSC frequency to ensure it always exceeds the minimum required. 2.15.2.1.3.
RP2040 Datasheet generators. It cannot be taken directly from the XIN or XOUT pins. 2.15.2.3. External Clocks If external clocks exist in your hardware design then they can be used to clock the RP2040 either on their own or in conjunction with the XOSC or ROSC. This will potentially save power and will allow components on the RP2040 to be run synchronously with external components to simplify data transfer between chips.
RP2040 Datasheet The PLLs are not affected by SLEEP mode. If the user wants to save power in SLEEP mode then all clock generators must be switched away from the PLLs and they must be stopped in software before entering SLEEP mode. The PLLs are not stopped and restarted automatically when entering and exiting DORMANT mode. If they are left running on entry to DORMANT mode they will be corrupted and will generate out of control clocks that will consume power unnecessarily.
RP2040 Datasheet 2.15.3.2. Multiplexers All clock generators have a multiplexer referred to as the auxiliary (aux) mux. This mux has a conventional design whose output will glitch when changing the select control. Two clock generators (clk_sys and clk_ref) have an additional multiplexer, referred to as the glitchless mux. The glitchless mux can switch between clock sources without generating a glitch on the output.
RP2040 Datasheet Figure 31. An example of fractional division. All dividers support on-the-fly divisor changes meaning the output clock will switch cleanly from one divisor to another. The clock generator does not need to be stopped during clock divisor changes. It does this by synchronising the divisor change to the end of the clock cycle. Similarly, the enable is synchronised to the end of the clock cycle so will not generate glitches when the clock generator is enabled or disabled.
RP2040 Datasheet registers, including those that control the clock enables. clk_sys_clocks does not have a wake mode enable because disabling it would prevent the cores from accessing the clocks control registers. The gpclks do not have clock enables. 2.15.3.5.2. System Sleep Mode System sleep mode is entered automatically when both cores are in sleep and the DMA has no outstanding transactions.
RP2040 Datasheet Interval Register Test Interval Accuracy 15 32 ms 62.5 Hz 2.15.5. Resus It is possible to write software that inadvertently stops clk_sys. This will normally cause an unrecoverable lock-up of the cores and the on-chip debugger, leaving the user unable to trace the problem. To mitigate against that, an automatic resuscitation circuit is provided which will switch clk_sys to a known good clock source if no edges are detected over a user-defined interval.
RP2040 Datasheet And also a struct to describe the registers of a clock generator: SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2040/hardware_structs/include/hardware/structs/clocks.
RP2040 Datasheet 81 asm volatile ( 82 ".syntax unified \n\t" 83 "1: \n\t" 84 "subs %0, #1 \n\t" 85 "bne 1b" 86 : "+r" (delay_cyc) 87 ); 88 89 } } 90 91 // Set aux mux first, and then glitchless mux if this clock has one 92 hw_write_masked(&clock->ctrl, 93 (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), 94 95 CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS ); 96 97 if (has_glitchless_mux(clk_index)) { 98 hw_write_masked(&clock->ctrl, 99 src << CLOCKS_CLK_REF_CTRL_SRC_LSB, 100 CLOCKS_CLK_REF_CTRL_
RP2040 Datasheet WARNING It is assumed the source frequency the programmer provides is correct. If it is not then the frequency returned by clock_get_hz will be inaccurate. 2.15.6.2. Using the frequency counter To use the frequency counter, the programmer must: • Set the reference frequency: clk_ref • Set the mux position of the source they want to measure.
RP2040 Datasheet NOTE The frequency counter can also be used in a test mode. This allows the hardware to check if the frequency is within a minimum frequency and a maximum frequency, set in FC0_MIN_KHZ and FC0_MAX_KHZ. In this mode, the PASS bit in FC0_STATUS will be set when DONE is set if the frequency is within the specified range. Otherwise, either the FAST or SLOW bit will be set. If the programmer attempts to count a stopped clock, or the clock stops running then the DIED bit will be set.
RP2040 Datasheet 379 if (has_glitchless_mux(clk_index)) { 380 // AUX src is always 1 381 src = 1; 382 } 383 384 // Set the GPIO function 385 gpio_set_function(gpio, GPIO_FUNC_GPCK); 386 387 // Now we have the src, auxsrc, and configured the gpio input 388 // call clock configure to run the clock from a gpio 389 return clock_configure(clk_index, src, auxsrc, src_freq, freq); 390 } 2.15.6.5. Enabling resus SDK: https://github.
RP2040 Datasheet NOTE clk_sys is always sent to proc0 and proc1 during sleep mode as some logic needs to be clocked for the processor to wake up again. Pico Extras: https://github.com/raspberrypi/pico-extras/tree/master/src/rp2_common/pico_sleep/sleep.
RP2040 Datasheet Offset Name Info 0x38 CLK_REF_SELECTED Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x3c CLK_SYS_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x40 CLK_SYS_DIV Clock divisor, can be changed on-the-fly 0x44 CLK_SYS_SELECTED Indicates which SRC is currently selected by the glitchless mux (one-hot).
RP2040 Datasheet Offset Name Info 0xa8 SLEEP_EN0 enable clock in sleep mode 0xac SLEEP_EN1 enable clock in sleep mode 0xb0 ENABLED0 indicates the state of the clock enable 0xb4 ENABLED1 indicates the state of the clock enable 0xb8 INTR Raw Interrupts 0xbc INTE Interrupt Enable 0xc0 INTF Interrupt Force 0xc4 INTS Interrupt status after masking & forcing CLOCKS: CLK_GPOUT0_CTRL Register Offset: 0x00 Description Clock control, can be changed on-the-fly (except for auxsrc) Table 219.
RP2040 Datasheet CLOCKS: CLK_GPOUT0_DIV Register Offset: 0x04 Description Clock divisor, can be changed on-the-fly Table 220. CLK_GPOUT0_DIV Register Bits Name Description Type Reset 31:8 INT Integer component of the divisor, 0 → divide by 2^16 RW 0x000001 7:0 FRAC Fractional component of the divisor RW 0x00 CLOCKS: CLK_GPOUT0_SELECTED Register Offset: 0x08 Description Indicates which SRC is currently selected by the glitchless mux (one-hot). Table 221.
RP2040 Datasheet Bits Name Description Type Reset 8:5 AUXSRC Selects the auxiliary clock source, will glitch when RW 0x0 - - switching 0x0 → clksrc_pll_sys 0x1 → clksrc_gpin0 0x2 → clksrc_gpin1 0x3 → clksrc_pll_usb 0x4 → rosc_clksrc 0x5 → xosc_clksrc 0x6 → clk_sys 0x7 → clk_usb 0x8 → clk_adc 0x9 → clk_rtc 0xa → clk_ref 4:0 Reserved. - CLOCKS: CLK_GPOUT1_DIV Register Offset: 0x10 Description Clock divisor, can be changed on-the-fly Table 223.
RP2040 Datasheet Bits Name Description Type 17:16 PHASE This delays the enable signal by up to 3 cycles of the input RW Reset 0x0 clock This must be set before the clock is enabled to have any effect 15:13 Reserved. - - - 12 DC50 Enables duty cycle correction for odd divisors RW 0x0 11 ENABLE Starts and stops the clock generator cleanly RW 0x0 10 KILL Asynchronously kills the clock generator RW 0x0 9 Reserved.
RP2040 Datasheet Description Clock control, can be changed on-the-fly (except for auxsrc) Table 228. CLK_GPOUT3_CTRL Register Bits Name Description Type Reset 31:21 Reserved. - - - 20 NUDGE An edge on this signal shifts the phase of the output by 1 RW 0x0 - - cycle of the input clock This can be done at any time 19:18 Reserved.
RP2040 Datasheet Description Indicates which SRC is currently selected by the glitchless mux (one-hot). Table 230. CLK_GPOUT3_SELECT ED Register Bits Description Type Reset 31:0 This slice does not have a glitchless mux (only the AUX_SRC field is present, RO 0x00000001 not SRC) so this register is hardwired to 0x1. CLOCKS: CLK_REF_CTRL Register Offset: 0x30 Description Clock control, can be changed on-the-fly (except for auxsrc) Table 231.
RP2040 Datasheet Table 233. CLK_REF_SELECTED Register Bits Description Type Reset 31:0 The glitchless multiplexer does not switch instantaneously (to avoid glitches), RO 0x00000001 so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux.
RP2040 Datasheet Table 236. CLK_SYS_SELECTED Register Bits Description Type Reset 31:0 The glitchless multiplexer does not switch instantaneously (to avoid glitches), RO 0x00000001 so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux.
RP2040 Datasheet Bits Name Description Type Reset 20 NUDGE An edge on this signal shifts the phase of the output by 1 RW 0x0 - - cycle of the input clock This can be done at any time 19:18 Reserved. - 17:16 PHASE This delays the enable signal by up to 3 cycles of the input RW 0x0 clock This must be set before the clock is enabled to have any effect 15:12 Reserved.
RP2040 Datasheet Table 241. CLK_USB_SELECTED Register Bits Description Type Reset 31:0 This slice does not have a glitchless mux (only the AUX_SRC field is present, RO 0x00000001 not SRC) so this register is hardwired to 0x1. CLOCKS: CLK_ADC_CTRL Register Offset: 0x60 Description Clock control, can be changed on-the-fly (except for auxsrc) Table 242. CLK_ADC_CTRL Register Bits Name Description Type Reset 31:21 Reserved.
RP2040 Datasheet Offset: 0x68 Description Indicates which SRC is currently selected by the glitchless mux (one-hot). Table 244. CLK_ADC_SELECTED Register Bits Description Type Reset 31:0 This slice does not have a glitchless mux (only the AUX_SRC field is present, RO 0x00000001 not SRC) so this register is hardwired to 0x1. CLOCKS: CLK_RTC_CTRL Register Offset: 0x6c Description Clock control, can be changed on-the-fly (except for auxsrc) Table 245.
RP2040 Datasheet Table 246. CLK_RTC_DIV Register Bits Name Description Type Reset 31:8 INT Integer component of the divisor, 0 → divide by 2^16 RW 0x000001 7:0 FRAC Fractional component of the divisor RW 0x00 CLOCKS: CLK_RTC_SELECTED Register Offset: 0x74 Description Indicates which SRC is currently selected by the glitchless mux (one-hot). Table 247.
RP2040 Datasheet Table 250. FC0_REF_KHZ Register Bits Description Type Reset 31:20 Reserved. - - 19:0 Reference clock frequency in kHz RW 0x00000 CLOCKS: FC0_MIN_KHZ Register Offset: 0x84 Table 251. FC0_MIN_KHZ Register Bits Description Type Reset 31:25 Reserved. - - 24:0 Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using RW 0x0000000 the pass/fail flags CLOCKS: FC0_MAX_KHZ Register Offset: 0x88 Table 252.
RP2040 Datasheet Table 255. FC0_SRC Register Bits Description Type Reset 31:8 Reserved.
RP2040 Datasheet Offset: 0x9c Description Result of frequency measurement, only valid when status_done=1 Table 257. FC0_RESULT Register Bits Name Description Type Reset 31:30 Reserved. - - - 29:5 KHZ RO 0x0000000 4:0 FRAC RO 0x00 Type Reset CLOCKS: WAKE_EN0 Register Offset: 0xa0 Description enable clock in wake mode Table 258. WAKE_EN0 Register 2.15.
RP2040 Datasheet Bits Name 7 Description Type Reset CLK_SYS_I2C1 RW 0x1 6 CLK_SYS_I2C0 RW 0x1 5 CLK_SYS_DMA RW 0x1 4 CLK_SYS_BUSFABRIC RW 0x1 3 CLK_SYS_BUSCTRL RW 0x1 2 CLK_SYS_ADC RW 0x1 1 CLK_ADC_ADC RW 0x1 0 CLK_SYS_CLOCKS RW 0x1 CLOCKS: WAKE_EN1 Register Offset: 0xa4 Description enable clock in wake mode Table 259. WAKE_EN1 Register Bits Name Description Type Reset 31:15 Reserved.
RP2040 Datasheet Bits Name 30 Description Type Reset CLK_SYS_SRAM2 RW 0x1 29 CLK_SYS_SRAM1 RW 0x1 28 CLK_SYS_SRAM0 RW 0x1 27 CLK_SYS_SPI1 RW 0x1 26 CLK_PERI_SPI1 RW 0x1 25 CLK_SYS_SPI0 RW 0x1 24 CLK_PERI_SPI0 RW 0x1 23 CLK_SYS_SIO RW 0x1 22 CLK_SYS_RTC RW 0x1 21 CLK_RTC_RTC RW 0x1 20 CLK_SYS_ROSC RW 0x1 19 CLK_SYS_ROM RW 0x1 18 CLK_SYS_RESETS RW 0x1 17 CLK_SYS_PWM RW 0x1 16 CLK_SYS_PSM RW 0x1 15 CLK_SYS_PLL_USB RW 0x1 14 CLK_SYS_PLL_SYS
RP2040 Datasheet Table 261. SLEEP_EN1 Register Bits Name Description Type Reset 31:15 Reserved.
RP2040 Datasheet Bits Name 17 Description Type Reset CLK_SYS_PWM RO 0x0 16 CLK_SYS_PSM RO 0x0 15 CLK_SYS_PLL_USB RO 0x0 14 CLK_SYS_PLL_SYS RO 0x0 13 CLK_SYS_PIO1 RO 0x0 12 CLK_SYS_PIO0 RO 0x0 11 CLK_SYS_PADS RO 0x0 10 CLK_SYS_VREG_AND_CHIP_RESET RO 0x0 9 CLK_SYS_JTAG RO 0x0 8 CLK_SYS_IO RO 0x0 7 CLK_SYS_I2C1 RO 0x0 6 CLK_SYS_I2C0 RO 0x0 5 CLK_SYS_DMA RO 0x0 4 CLK_SYS_BUSFABRIC RO 0x0 3 CLK_SYS_BUSCTRL RO 0x0 2 CLK_SYS_ADC RO 0x0 1 CLK_AD
RP2040 Datasheet Bits Name 3 Description Type Reset CLK_SYS_SYSINFO RO 0x0 2 CLK_SYS_SYSCFG RO 0x0 1 CLK_SYS_SRAM5 RO 0x0 0 CLK_SYS_SRAM4 RO 0x0 CLOCKS: INTR Register Offset: 0xb8 Description Raw Interrupts Table 264. INTR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLK_SYS_RESUS RO 0x0 CLOCKS: INTE Register Offset: 0xbc Description Interrupt Enable Table 265. INTE Register Bits Name Description Type Reset 31:1 Reserved.
RP2040 Datasheet Table 267. INTS Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLK_SYS_RESUS RO 0x0 2.16. Crystal Oscillator (XOSC) 2.16.1. Overview The Crystal Oscillator (XOSC) uses an external crystal to produce an accurate reference clock. The RP2040 supports 1MHz to 15MHz crystals and the RP2040 reference design (see Hardware design with RP2040, Minimal Design Example) uses a 12MHz crystal.
RP2040 Datasheet NOTE the value is rounded up to the nearest integer so the wait time will be just over 1ms 2.16.4. XOSC Counter The COUNT register provides a method of managing short software delays. Writing a value to the COUNT register automatically triggers it to start counting down to zero at the XOSC frequency. The programmer then simply polls the register until it reaches zero.
RP2040 Datasheet 19 io_rw_32 startup; 20 io_rw_32 _reserved[3]; 21 io_rw_32 count; 22 } xosc_hw_t; 23 24 #define xosc_hw ((xosc_hw_t *const)XOSC_BASE) SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_xosc/xosc.c Lines 27 - 39 27 void xosc_init(void) { 28 // Assumes 1-15 MHz input, checked above.
RP2040 Datasheet Bits Name Description Type Reset 23:12 ENABLE On power-up this field is initialised to DISABLE and the RW - RW - chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.
RP2040 Datasheet Table 271. DORMANT Register Bits Description Type Reset 31:0 This is used to save power by pausing the XOSC RW - On power-up this field is initialised to WAKE An invalid write will also select WAKE WARNING: stop the PLLs before selecting dormant mode WARNING: setup the irq before selecting dormant mode 0x636f6d61 → DORMANT 0x77616b65 → WAKE XOSC: STARTUP Register Offset: 0x0c Description Controls the startup delay Table 272.
RP2040 Datasheet start the Crystal Oscillator (XOSC) and PLLs. The ROSC can be disabled after the system clocks have been switched to the XOSC. Each oscillator has advantages and the programmer can switch between them to achieve the best solution for the application. Figure 34. ROSC overview. 2.17.2. ROSC/XOSC trade-offs The advantages of the ROSC are its flexibility and its low power. Also, there is no requirement for internal or external components when using the ROSC to provide clocks.
RP2040 Datasheet to shorten the ROSC loop, the bypassed stages still propagate the signal and therefore their drive strengths must be set to at least the same level as the lowest drive strength in the stages that are in the loop. This will not affect the oscillation frequency. 2.17.4. ROSC divider The ROSC frequency is too fast to be used directly so is divided in an integer divider controlled by the DIV register.
RP2040 Datasheet WARNING If no IRQ is configured before going into dormant mode the ROSC will never restart. See Section 2.11.5.2 for a some examples of dormant mode. 2.17.8. List of Registers The ROSC registers start at a base address of 0x40060000 (defined as ROSC_BASE in SDK). Table 274.
RP2040 Datasheet Bits Name Description Type Reset 11:0 FREQ_RANGE Controls the number of delay stages in the ROSC ring RW 0xaa0 LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 HIGH uses stages 0 to 3 TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes
RP2040 Datasheet Table 277. FREQB Register Bits Name Description Type Reset 31:16 PASSWD Set to 0x9696 to apply the settings RW 0x0000 Any other value in this field will set all drive strengths to 0 0x9696 → PASS 15 Reserved. - - - 14:12 DS7 Stage 7 drive strength RW 0x0 11 Reserved. - - - 10:8 DS6 Stage 6 drive strength RW 0x0 7 Reserved. - - - 6:4 DS5 Stage 5 drive strength RW 0x0 3 Reserved.
RP2040 Datasheet Table 280. PHASE Register Bits Name Description Type Reset 31:12 Reserved.
RP2040 Datasheet Table 283. COUNT Register Bits Description Type Reset 31:8 Reserved. - - 7:0 A down counter running at the ROSC frequency which counts to zero and RW 0x00 stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. 2.18. PLL 2.18.1. Overview The PLL is designed to take a reference clock, and multiply it using a VCO (Voltage Controlled Oscillator) with a feedback loop.
RP2040 Datasheet • Maximum input frequency (FREF / REFDIV) is VCO frequency divided by 16, due to minimum feedback divisor Additionally, the maximum frequencies of the chip’s clock generators (attached to FOUTPOSTDIV) must be respected. For the system PLL this is 133 MHz, and for the USB PLL, 48 MHz. NOTE The crystal oscillator on RP2040 is designed for crystals between 5 and 15 MHz, so typically REFDIV should be 1.
RP2040 Datasheet 13 # Fixed hardware parameters 14 fbdiv_range = range(16, 320 + 1) 15 postdiv_range = range(1, 7 + 1) 16 17 best = (0, 0, 0, 0) 18 best_margin = args.output 19 20 for fbdiv in (fbdiv_range if args.low_vco else reversed(fbdiv_range)): 21 vco = args.input * fbdiv 22 if vco < args.vco_min or vco > args.
RP2040 Datasheet PD2: 2 We can restrict the search to lower VCO frequencies, so that the script will consider looser frequency matches. Note that, whilst a 500 MHz VCO would be ideal here, we can’t achieve exactly 500 MHz by multiplying the 12 MHz input by an integer, which is why the previous invocation returned such a high VCO frequency. $ ./vcocalc.py -l 125 --vco-max 600 Requested: 125.0 MHz Achieved: 126.
RP2040 Datasheet refclk) 18 uint32_t fbdiv = vco_freq / (ref_mhz * MHZ); The programming sequence for the PLL is as follows: • Program the reference clock divider (is a divide by 1 in the RP2040 case) • Program the feedback divider • Turn on the main power and VCO • Wait for the VCO to lock (i.e. keep its output frequency stable) • Set up post dividers and turn them on SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_pll/pll.
RP2040 Datasheet Offset Name Info 0x4 PWR Controls the PLL power modes. 0x8 FBDIV_INT Feedback divisor 0xc PRIM Controls the PLL post dividers for the primary output PLL: CS Register Offset: 0x0 Description Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=400MHz, max=1600MHz Table 285. CS Register Bits Name Description Type Reset 31 LOCK PLL is locked RO 0x0 30:9 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 0 PD PLL powerdown RW 0x1 To save power set high when PLL output not required. PLL: FBDIV_INT Register Offset: 0x8 Description Feedback divisor (note: this PLL does not support fractional division) Table 287. FBDIV_INT Register Bits Description Type Reset 31:12 Reserved.
RP2040 Datasheet • 2 x I2C (two-wire serial interface) - Section 4.3, “I2C” • 8 x two-channel PWM - Section 4.5, “PWM” • 2 x external clock inputs - Section 2.15.2.3, “External Clocks” • 4 x general purpose clock output - Section 2.15, “Clocks” • 4 x input to ADC - Section 4.9, “ADC and Temperature Sensor” • USB VBUS management - Section 4.1.2.
RP2040 Datasheet Function 10 SPI1 SCK UART1 CTS I2C1 SDA PWM5 A SIO PIO0 PIO1 USB VBUS DET 11 SPI1 TX UART1 RTS I2C1 SCL PWM5 B SIO PIO0 PIO1 USB VBUS EN 12 SPI1 RX UART0 TX I2C0 SDA PWM6 A SIO PIO0 PIO1 USB OVCUR DET 13 SPI1 CSn UART0 RX I2C0 SCL PWM6 B SIO PIO0 PIO1 USB VBUS DET 14 SPI1 SCK UART0 CTS I2C1 SDA PWM7 A SIO PIO0 PIO1 USB VBUS EN 15 SPI1 TX UART0 RTS I2C1 SCL PWM7 B SIO PIO0 PIO1 USB OVCUR DET 16 SPI0 RX UART0 TX I2C0 SDA PWM0 A SIO
RP2040 Datasheet Function Name Description CLOCK GPINx General purpose clock inputs. Can be routed to a number of internal clock domains on RP2040, e.g. to provide a 1 Hz clock for the RTC, or can be connected to an internal frequency counter. CLOCK GPOUTx General purpose clock outputs. Can drive a number of internal clocks onto GPIOs, with optional integer divide. USB OVCUR DET/VBUS USB power control signals to/from the internal USB controller DET/VBUS EN Table 291.
RP2040 Datasheet proc 0 the registers are enable (PROC0_INTE0), status (PROC0_INTS0), and force (PROC0_INTF0) . Dormant wake is used to wake the ROSC or XOSC up from dormant mode. See Section 2.11.5.2 for more information on dormant mode.
RP2040 Datasheet WARNING Using IOVDD voltages greater than 1.8V, with the input thresholds set for 1.8V may result in damage to the chip. Pad input threshold are adjusted on a per bank basis, with separate VOLTAGE_SELECT registers for the pads associated with the User IO bank (IO Bank 0) and the QSPI IO bank. However, both banks share the same digital IO supply (IOVDD), so both register should always be set to the same value. Pad register details are available in Section 2.19.6.
RP2040 Datasheet 41 } 2.19.5.2. Enable a GPIO interrupt The SDK provides a method of being interrupted when a GPIO pin changes state: SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_gpio/gpio.c Lines 171 - 177 171 void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled) { 172 // Separate mask/force/status per-core, so check which core called, and 173 // set the relevant IRQ controls.
RP2040 Datasheet 18 gpio_event_string(event_str, events); 19 printf("GPIO %d %s\n", gpio, event_str); 20 } 21 22 int main() { 23 stdio_init_all(); 24 25 printf("Hello GPIO IRQ\n"); 26 gpio_set_irq_enabled_with_callback(2, GPIO_IRQ_EDGE_RISE | GPIO_IRQ_EDGE_FALL, true, &gpio_callback); 27 28 // Wait forever 29 while (1); 30 31 return 0; 32 } 33 34 35 static const char *gpio_irq_str[] = { 36 "LEVEL_LOW", 37 "LEVEL_HIGH", // 0x2 // 0x1 38 "EDGE_FALL", // 0x4 39 "EDGE_RISE" // 0x8 40
RP2040 Datasheet 2.19. GPIO Offset Name Info 0x00c GPIO1_CTRL GPIO control including function select and overrides. 0x010 GPIO2_STATUS GPIO status 0x014 GPIO2_CTRL GPIO control including function select and overrides. 0x018 GPIO3_STATUS GPIO status 0x01c GPIO3_CTRL GPIO control including function select and overrides. 0x020 GPIO4_STATUS GPIO status 0x024 GPIO4_CTRL GPIO control including function select and overrides.
RP2040 Datasheet 2.19. GPIO Offset Name Info 0x09c GPIO19_CTRL GPIO control including function select and overrides. 0x0a0 GPIO20_STATUS GPIO status 0x0a4 GPIO20_CTRL GPIO control including function select and overrides. 0x0a8 GPIO21_STATUS GPIO status 0x0ac GPIO21_CTRL GPIO control including function select and overrides. 0x0b0 GPIO22_STATUS GPIO status 0x0b4 GPIO22_CTRL GPIO control including function select and overrides.
RP2040 Datasheet Offset Name Info 0x12c PROC0_INTS3 Interrupt status after masking & forcing for proc0 0x130 PROC1_INTE0 Interrupt Enable for proc1 0x134 PROC1_INTE1 Interrupt Enable for proc1 0x138 PROC1_INTE2 Interrupt Enable for proc1 0x13c PROC1_INTE3 Interrupt Enable for proc1 0x140 PROC1_INTF0 Interrupt Force for proc1 0x144 PROC1_INTF1 Interrupt Force for proc1 0x148 PROC1_INTF2 Interrupt Force for proc1 0x14c PROC1_INTF3 Interrupt Force for proc1 0x150 PROC1_INTS0 In
RP2040 Datasheet Bits Name Description Type Reset 23:20 Reserved. - - - 19 INTOPERI input signal to peripheral, after override is applied RO 0x0 18 Reserved. - - - 17 INFROMPAD input signal from pad, before override is applied RO 0x0 16:14 Reserved. - - - 13 OETOPAD output enable to pad after register override is applied RO 0x0 12 OEFROMPERI output enable from selected peripheral, before register RO 0x0 override is applied 11:10 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 9:8 OUTOVER 0x0 → drive output from peripheral signal selected by RW 0x0 funcsel 0x1 → drive output from inverse of peripheral signal selected by funcsel 0x2 → drive output low 0x3 → drive output high 7:5 Reserved. - - - 4:0 FUNCSEL Function select. 31 == NULL. See GPIO function table for RW 0x1f available functions. IO_BANK0: INTR0 Register Offset: 0x0f0 Description Raw Interrupts Table 296. INTR0 Register 2.19.
RP2040 Datasheet Bits Name 8 Description Type Reset GPIO2_LEVEL_LOW RO 0x0 7 GPIO1_EDGE_HIGH WC 0x0 6 GPIO1_EDGE_LOW WC 0x0 5 GPIO1_LEVEL_HIGH RO 0x0 4 GPIO1_LEVEL_LOW RO 0x0 3 GPIO0_EDGE_HIGH WC 0x0 2 GPIO0_EDGE_LOW WC 0x0 1 GPIO0_LEVEL_HIGH RO 0x0 0 GPIO0_LEVEL_LOW RO 0x0 Type Reset IO_BANK0: INTR1 Register Offset: 0x0f4 Description Raw Interrupts Table 297. INTR1 Register 2.19.
RP2040 Datasheet Bits Name 10 Description Type Reset GPIO10_EDGE_LOW WC 0x0 9 GPIO10_LEVEL_HIGH RO 0x0 8 GPIO10_LEVEL_LOW RO 0x0 7 GPIO9_EDGE_HIGH WC 0x0 6 GPIO9_EDGE_LOW WC 0x0 5 GPIO9_LEVEL_HIGH RO 0x0 4 GPIO9_LEVEL_LOW RO 0x0 3 GPIO8_EDGE_HIGH WC 0x0 2 GPIO8_EDGE_LOW WC 0x0 1 GPIO8_LEVEL_HIGH RO 0x0 0 GPIO8_LEVEL_LOW RO 0x0 Type Reset IO_BANK0: INTR2 Register Offset: 0x0f8 Description Raw Interrupts Table 298. INTR2 Register 2.19.
RP2040 Datasheet Bits Name 12 Description Type Reset GPIO19_LEVEL_LOW RO 0x0 11 GPIO18_EDGE_HIGH WC 0x0 10 GPIO18_EDGE_LOW WC 0x0 9 GPIO18_LEVEL_HIGH RO 0x0 8 GPIO18_LEVEL_LOW RO 0x0 7 GPIO17_EDGE_HIGH WC 0x0 6 GPIO17_EDGE_LOW WC 0x0 5 GPIO17_LEVEL_HIGH RO 0x0 4 GPIO17_LEVEL_LOW RO 0x0 3 GPIO16_EDGE_HIGH WC 0x0 2 GPIO16_EDGE_LOW WC 0x0 1 GPIO16_LEVEL_HIGH RO 0x0 0 GPIO16_LEVEL_LOW RO 0x0 IO_BANK0: INTR3 Register Offset: 0x0fc Description Raw Interrup
RP2040 Datasheet Bits Name 7 Description Type Reset GPIO25_EDGE_HIGH WC 0x0 6 GPIO25_EDGE_LOW WC 0x0 5 GPIO25_LEVEL_HIGH RO 0x0 4 GPIO25_LEVEL_LOW RO 0x0 3 GPIO24_EDGE_HIGH WC 0x0 2 GPIO24_EDGE_LOW WC 0x0 1 GPIO24_LEVEL_HIGH RO 0x0 0 GPIO24_LEVEL_LOW RO 0x0 Type Reset IO_BANK0: PROC0_INTE0 Register Offset: 0x100 Description Interrupt Enable for proc0 Table 300. PROC0_INTE0 Register 2.19.
RP2040 Datasheet Bits Name 9 Description Type Reset GPIO2_LEVEL_HIGH RW 0x0 8 GPIO2_LEVEL_LOW RW 0x0 7 GPIO1_EDGE_HIGH RW 0x0 6 GPIO1_EDGE_LOW RW 0x0 5 GPIO1_LEVEL_HIGH RW 0x0 4 GPIO1_LEVEL_LOW RW 0x0 3 GPIO0_EDGE_HIGH RW 0x0 2 GPIO0_EDGE_LOW RW 0x0 1 GPIO0_LEVEL_HIGH RW 0x0 0 GPIO0_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC0_INTE1 Register Offset: 0x104 Description Interrupt Enable for proc0 Table 301. PROC0_INTE1 Register 2.19.
RP2040 Datasheet Bits Name 11 Description Type Reset GPIO10_EDGE_HIGH RW 0x0 10 GPIO10_EDGE_LOW RW 0x0 9 GPIO10_LEVEL_HIGH RW 0x0 8 GPIO10_LEVEL_LOW RW 0x0 7 GPIO9_EDGE_HIGH RW 0x0 6 GPIO9_EDGE_LOW RW 0x0 5 GPIO9_LEVEL_HIGH RW 0x0 4 GPIO9_LEVEL_LOW RW 0x0 3 GPIO8_EDGE_HIGH RW 0x0 2 GPIO8_EDGE_LOW RW 0x0 1 GPIO8_LEVEL_HIGH RW 0x0 0 GPIO8_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC0_INTE2 Register Offset: 0x108 Description Interrupt Enable for proc0 Table
RP2040 Datasheet Bits Name 13 Description Type Reset GPIO19_LEVEL_HIGH RW 0x0 12 GPIO19_LEVEL_LOW RW 0x0 11 GPIO18_EDGE_HIGH RW 0x0 10 GPIO18_EDGE_LOW RW 0x0 9 GPIO18_LEVEL_HIGH RW 0x0 8 GPIO18_LEVEL_LOW RW 0x0 7 GPIO17_EDGE_HIGH RW 0x0 6 GPIO17_EDGE_LOW RW 0x0 5 GPIO17_LEVEL_HIGH RW 0x0 4 GPIO17_LEVEL_LOW RW 0x0 3 GPIO16_EDGE_HIGH RW 0x0 2 GPIO16_EDGE_LOW RW 0x0 1 GPIO16_LEVEL_HIGH RW 0x0 0 GPIO16_LEVEL_LOW RW 0x0 IO_BANK0: PROC0_INTE3 Register
RP2040 Datasheet Bits Name 8 Description Type Reset GPIO26_LEVEL_LOW RW 0x0 7 GPIO25_EDGE_HIGH RW 0x0 6 GPIO25_EDGE_LOW RW 0x0 5 GPIO25_LEVEL_HIGH RW 0x0 4 GPIO25_LEVEL_LOW RW 0x0 3 GPIO24_EDGE_HIGH RW 0x0 2 GPIO24_EDGE_LOW RW 0x0 1 GPIO24_LEVEL_HIGH RW 0x0 0 GPIO24_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC0_INTF0 Register Offset: 0x110 Description Interrupt Force for proc0 Table 304. PROC0_INTF0 Register 2.19.
RP2040 Datasheet Bits Name 10 Description Type Reset GPIO2_EDGE_LOW RW 0x0 9 GPIO2_LEVEL_HIGH RW 0x0 8 GPIO2_LEVEL_LOW RW 0x0 7 GPIO1_EDGE_HIGH RW 0x0 6 GPIO1_EDGE_LOW RW 0x0 5 GPIO1_LEVEL_HIGH RW 0x0 4 GPIO1_LEVEL_LOW RW 0x0 3 GPIO0_EDGE_HIGH RW 0x0 2 GPIO0_EDGE_LOW RW 0x0 1 GPIO0_LEVEL_HIGH RW 0x0 0 GPIO0_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC0_INTF1 Register Offset: 0x114 Description Interrupt Force for proc0 Table 305. PROC0_INTF1 Register 2.19.
RP2040 Datasheet Bits Name 12 Description Type Reset GPIO11_LEVEL_LOW RW 0x0 11 GPIO10_EDGE_HIGH RW 0x0 10 GPIO10_EDGE_LOW RW 0x0 9 GPIO10_LEVEL_HIGH RW 0x0 8 GPIO10_LEVEL_LOW RW 0x0 7 GPIO9_EDGE_HIGH RW 0x0 6 GPIO9_EDGE_LOW RW 0x0 5 GPIO9_LEVEL_HIGH RW 0x0 4 GPIO9_LEVEL_LOW RW 0x0 3 GPIO8_EDGE_HIGH RW 0x0 2 GPIO8_EDGE_LOW RW 0x0 1 GPIO8_LEVEL_HIGH RW 0x0 0 GPIO8_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC0_INTF2 Register Offset: 0x118 Description I
RP2040 Datasheet Bits Name 14 Description Type Reset GPIO19_EDGE_LOW RW 0x0 13 GPIO19_LEVEL_HIGH RW 0x0 12 GPIO19_LEVEL_LOW RW 0x0 11 GPIO18_EDGE_HIGH RW 0x0 10 GPIO18_EDGE_LOW RW 0x0 9 GPIO18_LEVEL_HIGH RW 0x0 8 GPIO18_LEVEL_LOW RW 0x0 7 GPIO17_EDGE_HIGH RW 0x0 6 GPIO17_EDGE_LOW RW 0x0 5 GPIO17_LEVEL_HIGH RW 0x0 4 GPIO17_LEVEL_LOW RW 0x0 3 GPIO16_EDGE_HIGH RW 0x0 2 GPIO16_EDGE_LOW RW 0x0 1 GPIO16_LEVEL_HIGH RW 0x0 0 GPIO16_LEVEL_LOW RW 0x0 I
RP2040 Datasheet Bits Name 9 Description Type Reset GPIO26_LEVEL_HIGH RW 0x0 8 GPIO26_LEVEL_LOW RW 0x0 7 GPIO25_EDGE_HIGH RW 0x0 6 GPIO25_EDGE_LOW RW 0x0 5 GPIO25_LEVEL_HIGH RW 0x0 4 GPIO25_LEVEL_LOW RW 0x0 3 GPIO24_EDGE_HIGH RW 0x0 2 GPIO24_EDGE_LOW RW 0x0 1 GPIO24_LEVEL_HIGH RW 0x0 0 GPIO24_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC0_INTS0 Register Offset: 0x120 Description Interrupt status after masking & forcing for proc0 Table 308.
RP2040 Datasheet Bits Name 11 Description Type Reset GPIO2_EDGE_HIGH RO 0x0 10 GPIO2_EDGE_LOW RO 0x0 9 GPIO2_LEVEL_HIGH RO 0x0 8 GPIO2_LEVEL_LOW RO 0x0 7 GPIO1_EDGE_HIGH RO 0x0 6 GPIO1_EDGE_LOW RO 0x0 5 GPIO1_LEVEL_HIGH RO 0x0 4 GPIO1_LEVEL_LOW RO 0x0 3 GPIO0_EDGE_HIGH RO 0x0 2 GPIO0_EDGE_LOW RO 0x0 1 GPIO0_LEVEL_HIGH RO 0x0 0 GPIO0_LEVEL_LOW RO 0x0 Type Reset IO_BANK0: PROC0_INTS1 Register Offset: 0x124 Description Interrupt status after masking & for
RP2040 Datasheet Bits Name 13 Description Type Reset GPIO11_LEVEL_HIGH RO 0x0 12 GPIO11_LEVEL_LOW RO 0x0 11 GPIO10_EDGE_HIGH RO 0x0 10 GPIO10_EDGE_LOW RO 0x0 9 GPIO10_LEVEL_HIGH RO 0x0 8 GPIO10_LEVEL_LOW RO 0x0 7 GPIO9_EDGE_HIGH RO 0x0 6 GPIO9_EDGE_LOW RO 0x0 5 GPIO9_LEVEL_HIGH RO 0x0 4 GPIO9_LEVEL_LOW RO 0x0 3 GPIO8_EDGE_HIGH RO 0x0 2 GPIO8_EDGE_LOW RO 0x0 1 GPIO8_LEVEL_HIGH RO 0x0 0 GPIO8_LEVEL_LOW RO 0x0 Type Reset IO_BANK0: PROC0_INTS2 Regi
RP2040 Datasheet Bits Name 15 Description Type Reset GPIO19_EDGE_HIGH RO 0x0 14 GPIO19_EDGE_LOW RO 0x0 13 GPIO19_LEVEL_HIGH RO 0x0 12 GPIO19_LEVEL_LOW RO 0x0 11 GPIO18_EDGE_HIGH RO 0x0 10 GPIO18_EDGE_LOW RO 0x0 9 GPIO18_LEVEL_HIGH RO 0x0 8 GPIO18_LEVEL_LOW RO 0x0 7 GPIO17_EDGE_HIGH RO 0x0 6 GPIO17_EDGE_LOW RO 0x0 5 GPIO17_LEVEL_HIGH RO 0x0 4 GPIO17_LEVEL_LOW RO 0x0 3 GPIO16_EDGE_HIGH RO 0x0 2 GPIO16_EDGE_LOW RO 0x0 1 GPIO16_LEVEL_HIGH RO 0x0
RP2040 Datasheet Bits Name 10 Description Type Reset GPIO26_EDGE_LOW RO 0x0 9 GPIO26_LEVEL_HIGH RO 0x0 8 GPIO26_LEVEL_LOW RO 0x0 7 GPIO25_EDGE_HIGH RO 0x0 6 GPIO25_EDGE_LOW RO 0x0 5 GPIO25_LEVEL_HIGH RO 0x0 4 GPIO25_LEVEL_LOW RO 0x0 3 GPIO24_EDGE_HIGH RO 0x0 2 GPIO24_EDGE_LOW RO 0x0 1 GPIO24_LEVEL_HIGH RO 0x0 0 GPIO24_LEVEL_LOW RO 0x0 Type Reset IO_BANK0: PROC1_INTE0 Register Offset: 0x130 Description Interrupt Enable for proc1 Table 312.
RP2040 Datasheet Bits Name 12 Description Type Reset GPIO3_LEVEL_LOW RW 0x0 11 GPIO2_EDGE_HIGH RW 0x0 10 GPIO2_EDGE_LOW RW 0x0 9 GPIO2_LEVEL_HIGH RW 0x0 8 GPIO2_LEVEL_LOW RW 0x0 7 GPIO1_EDGE_HIGH RW 0x0 6 GPIO1_EDGE_LOW RW 0x0 5 GPIO1_LEVEL_HIGH RW 0x0 4 GPIO1_LEVEL_LOW RW 0x0 3 GPIO0_EDGE_HIGH RW 0x0 2 GPIO0_EDGE_LOW RW 0x0 1 GPIO0_LEVEL_HIGH RW 0x0 0 GPIO0_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC1_INTE1 Register Offset: 0x134 Description Interr
RP2040 Datasheet Bits Name 14 Description Type Reset GPIO11_EDGE_LOW RW 0x0 13 GPIO11_LEVEL_HIGH RW 0x0 12 GPIO11_LEVEL_LOW RW 0x0 11 GPIO10_EDGE_HIGH RW 0x0 10 GPIO10_EDGE_LOW RW 0x0 9 GPIO10_LEVEL_HIGH RW 0x0 8 GPIO10_LEVEL_LOW RW 0x0 7 GPIO9_EDGE_HIGH RW 0x0 6 GPIO9_EDGE_LOW RW 0x0 5 GPIO9_LEVEL_HIGH RW 0x0 4 GPIO9_LEVEL_LOW RW 0x0 3 GPIO8_EDGE_HIGH RW 0x0 2 GPIO8_EDGE_LOW RW 0x0 1 GPIO8_LEVEL_HIGH RW 0x0 0 GPIO8_LEVEL_LOW RW 0x0 Type Res
RP2040 Datasheet Bits Name 16 Description Type Reset GPIO20_LEVEL_LOW RW 0x0 15 GPIO19_EDGE_HIGH RW 0x0 14 GPIO19_EDGE_LOW RW 0x0 13 GPIO19_LEVEL_HIGH RW 0x0 12 GPIO19_LEVEL_LOW RW 0x0 11 GPIO18_EDGE_HIGH RW 0x0 10 GPIO18_EDGE_LOW RW 0x0 9 GPIO18_LEVEL_HIGH RW 0x0 8 GPIO18_LEVEL_LOW RW 0x0 7 GPIO17_EDGE_HIGH RW 0x0 6 GPIO17_EDGE_LOW RW 0x0 5 GPIO17_LEVEL_HIGH RW 0x0 4 GPIO17_LEVEL_LOW RW 0x0 3 GPIO16_EDGE_HIGH RW 0x0 2 GPIO16_EDGE_LOW RW 0x0
RP2040 Datasheet Bits Name 11 Description Type Reset GPIO26_EDGE_HIGH RW 0x0 10 GPIO26_EDGE_LOW RW 0x0 9 GPIO26_LEVEL_HIGH RW 0x0 8 GPIO26_LEVEL_LOW RW 0x0 7 GPIO25_EDGE_HIGH RW 0x0 6 GPIO25_EDGE_LOW RW 0x0 5 GPIO25_LEVEL_HIGH RW 0x0 4 GPIO25_LEVEL_LOW RW 0x0 3 GPIO24_EDGE_HIGH RW 0x0 2 GPIO24_EDGE_LOW RW 0x0 1 GPIO24_LEVEL_HIGH RW 0x0 0 GPIO24_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC1_INTF0 Register Offset: 0x140 Description Interrupt Force for proc
RP2040 Datasheet Bits Name 13 Description Type Reset GPIO3_LEVEL_HIGH RW 0x0 12 GPIO3_LEVEL_LOW RW 0x0 11 GPIO2_EDGE_HIGH RW 0x0 10 GPIO2_EDGE_LOW RW 0x0 9 GPIO2_LEVEL_HIGH RW 0x0 8 GPIO2_LEVEL_LOW RW 0x0 7 GPIO1_EDGE_HIGH RW 0x0 6 GPIO1_EDGE_LOW RW 0x0 5 GPIO1_LEVEL_HIGH RW 0x0 4 GPIO1_LEVEL_LOW RW 0x0 3 GPIO0_EDGE_HIGH RW 0x0 2 GPIO0_EDGE_LOW RW 0x0 1 GPIO0_LEVEL_HIGH RW 0x0 0 GPIO0_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC1_INTF1 Register O
RP2040 Datasheet Bits Name 15 Description Type Reset GPIO11_EDGE_HIGH RW 0x0 14 GPIO11_EDGE_LOW RW 0x0 13 GPIO11_LEVEL_HIGH RW 0x0 12 GPIO11_LEVEL_LOW RW 0x0 11 GPIO10_EDGE_HIGH RW 0x0 10 GPIO10_EDGE_LOW RW 0x0 9 GPIO10_LEVEL_HIGH RW 0x0 8 GPIO10_LEVEL_LOW RW 0x0 7 GPIO9_EDGE_HIGH RW 0x0 6 GPIO9_EDGE_LOW RW 0x0 5 GPIO9_LEVEL_HIGH RW 0x0 4 GPIO9_LEVEL_LOW RW 0x0 3 GPIO8_EDGE_HIGH RW 0x0 2 GPIO8_EDGE_LOW RW 0x0 1 GPIO8_LEVEL_HIGH RW 0x0 0 GPIO
RP2040 Datasheet Bits Name 17 Description Type Reset GPIO20_LEVEL_HIGH RW 0x0 16 GPIO20_LEVEL_LOW RW 0x0 15 GPIO19_EDGE_HIGH RW 0x0 14 GPIO19_EDGE_LOW RW 0x0 13 GPIO19_LEVEL_HIGH RW 0x0 12 GPIO19_LEVEL_LOW RW 0x0 11 GPIO18_EDGE_HIGH RW 0x0 10 GPIO18_EDGE_LOW RW 0x0 9 GPIO18_LEVEL_HIGH RW 0x0 8 GPIO18_LEVEL_LOW RW 0x0 7 GPIO17_EDGE_HIGH RW 0x0 6 GPIO17_EDGE_LOW RW 0x0 5 GPIO17_LEVEL_HIGH RW 0x0 4 GPIO17_LEVEL_LOW RW 0x0 3 GPIO16_EDGE_HIGH RW 0x
RP2040 Datasheet Bits Name 12 Description Type Reset GPIO27_LEVEL_LOW RW 0x0 11 GPIO26_EDGE_HIGH RW 0x0 10 GPIO26_EDGE_LOW RW 0x0 9 GPIO26_LEVEL_HIGH RW 0x0 8 GPIO26_LEVEL_LOW RW 0x0 7 GPIO25_EDGE_HIGH RW 0x0 6 GPIO25_EDGE_LOW RW 0x0 5 GPIO25_LEVEL_HIGH RW 0x0 4 GPIO25_LEVEL_LOW RW 0x0 3 GPIO24_EDGE_HIGH RW 0x0 2 GPIO24_EDGE_LOW RW 0x0 1 GPIO24_LEVEL_HIGH RW 0x0 0 GPIO24_LEVEL_LOW RW 0x0 Type Reset IO_BANK0: PROC1_INTS0 Register Offset: 0x150 Descr
RP2040 Datasheet Bits Name 14 Description Type Reset GPIO3_EDGE_LOW RO 0x0 13 GPIO3_LEVEL_HIGH RO 0x0 12 GPIO3_LEVEL_LOW RO 0x0 11 GPIO2_EDGE_HIGH RO 0x0 10 GPIO2_EDGE_LOW RO 0x0 9 GPIO2_LEVEL_HIGH RO 0x0 8 GPIO2_LEVEL_LOW RO 0x0 7 GPIO1_EDGE_HIGH RO 0x0 6 GPIO1_EDGE_LOW RO 0x0 5 GPIO1_LEVEL_HIGH RO 0x0 4 GPIO1_LEVEL_LOW RO 0x0 3 GPIO0_EDGE_HIGH RO 0x0 2 GPIO0_EDGE_LOW RO 0x0 1 GPIO0_LEVEL_HIGH RO 0x0 0 GPIO0_LEVEL_LOW RO 0x0 Type Reset IO_
RP2040 Datasheet Bits Name 16 Description Type Reset GPIO12_LEVEL_LOW RO 0x0 15 GPIO11_EDGE_HIGH RO 0x0 14 GPIO11_EDGE_LOW RO 0x0 13 GPIO11_LEVEL_HIGH RO 0x0 12 GPIO11_LEVEL_LOW RO 0x0 11 GPIO10_EDGE_HIGH RO 0x0 10 GPIO10_EDGE_LOW RO 0x0 9 GPIO10_LEVEL_HIGH RO 0x0 8 GPIO10_LEVEL_LOW RO 0x0 7 GPIO9_EDGE_HIGH RO 0x0 6 GPIO9_EDGE_LOW RO 0x0 5 GPIO9_LEVEL_HIGH RO 0x0 4 GPIO9_LEVEL_LOW RO 0x0 3 GPIO8_EDGE_HIGH RO 0x0 2 GPIO8_EDGE_LOW RO 0x0 1 GPI
RP2040 Datasheet Bits Name 18 Description Type Reset GPIO20_EDGE_LOW RO 0x0 17 GPIO20_LEVEL_HIGH RO 0x0 16 GPIO20_LEVEL_LOW RO 0x0 15 GPIO19_EDGE_HIGH RO 0x0 14 GPIO19_EDGE_LOW RO 0x0 13 GPIO19_LEVEL_HIGH RO 0x0 12 GPIO19_LEVEL_LOW RO 0x0 11 GPIO18_EDGE_HIGH RO 0x0 10 GPIO18_EDGE_LOW RO 0x0 9 GPIO18_LEVEL_HIGH RO 0x0 8 GPIO18_LEVEL_LOW RO 0x0 7 GPIO17_EDGE_HIGH RO 0x0 6 GPIO17_EDGE_LOW RO 0x0 5 GPIO17_LEVEL_HIGH RO 0x0 4 GPIO17_LEVEL_LOW RO 0x
RP2040 Datasheet Bits Name 13 Description Type Reset GPIO27_LEVEL_HIGH RO 0x0 12 GPIO27_LEVEL_LOW RO 0x0 11 GPIO26_EDGE_HIGH RO 0x0 10 GPIO26_EDGE_LOW RO 0x0 9 GPIO26_LEVEL_HIGH RO 0x0 8 GPIO26_LEVEL_LOW RO 0x0 7 GPIO25_EDGE_HIGH RO 0x0 6 GPIO25_EDGE_LOW RO 0x0 5 GPIO25_LEVEL_HIGH RO 0x0 4 GPIO25_LEVEL_LOW RO 0x0 3 GPIO24_EDGE_HIGH RO 0x0 2 GPIO24_EDGE_LOW RO 0x0 1 GPIO24_LEVEL_HIGH RO 0x0 0 GPIO24_LEVEL_LOW RO 0x0 Type Reset IO_BANK0: DORMANT_
RP2040 Datasheet Bits Name 15 Description Type Reset GPIO3_EDGE_HIGH RW 0x0 14 GPIO3_EDGE_LOW RW 0x0 13 GPIO3_LEVEL_HIGH RW 0x0 12 GPIO3_LEVEL_LOW RW 0x0 11 GPIO2_EDGE_HIGH RW 0x0 10 GPIO2_EDGE_LOW RW 0x0 9 GPIO2_LEVEL_HIGH RW 0x0 8 GPIO2_LEVEL_LOW RW 0x0 7 GPIO1_EDGE_HIGH RW 0x0 6 GPIO1_EDGE_LOW RW 0x0 5 GPIO1_LEVEL_HIGH RW 0x0 4 GPIO1_LEVEL_LOW RW 0x0 3 GPIO0_EDGE_HIGH RW 0x0 2 GPIO0_EDGE_LOW RW 0x0 1 GPIO0_LEVEL_HIGH RW 0x0 0 GPIO0_LEVEL_
RP2040 Datasheet Bits Name 17 Description Type Reset GPIO12_LEVEL_HIGH RW 0x0 16 GPIO12_LEVEL_LOW RW 0x0 15 GPIO11_EDGE_HIGH RW 0x0 14 GPIO11_EDGE_LOW RW 0x0 13 GPIO11_LEVEL_HIGH RW 0x0 12 GPIO11_LEVEL_LOW RW 0x0 11 GPIO10_EDGE_HIGH RW 0x0 10 GPIO10_EDGE_LOW RW 0x0 9 GPIO10_LEVEL_HIGH RW 0x0 8 GPIO10_LEVEL_LOW RW 0x0 7 GPIO9_EDGE_HIGH RW 0x0 6 GPIO9_EDGE_LOW RW 0x0 5 GPIO9_LEVEL_HIGH RW 0x0 4 GPIO9_LEVEL_LOW RW 0x0 3 GPIO8_EDGE_HIGH RW 0x0 2
RP2040 Datasheet Bits Name 19 Description Type Reset GPIO20_EDGE_HIGH RW 0x0 18 GPIO20_EDGE_LOW RW 0x0 17 GPIO20_LEVEL_HIGH RW 0x0 16 GPIO20_LEVEL_LOW RW 0x0 15 GPIO19_EDGE_HIGH RW 0x0 14 GPIO19_EDGE_LOW RW 0x0 13 GPIO19_LEVEL_HIGH RW 0x0 12 GPIO19_LEVEL_LOW RW 0x0 11 GPIO18_EDGE_HIGH RW 0x0 10 GPIO18_EDGE_LOW RW 0x0 9 GPIO18_LEVEL_HIGH RW 0x0 8 GPIO18_LEVEL_LOW RW 0x0 7 GPIO17_EDGE_HIGH RW 0x0 6 GPIO17_EDGE_LOW RW 0x0 5 GPIO17_LEVEL_HIGH RW 0
RP2040 Datasheet Bits Name 14 Description Type Reset GPIO27_EDGE_LOW RW 0x0 13 GPIO27_LEVEL_HIGH RW 0x0 12 GPIO27_LEVEL_LOW RW 0x0 11 GPIO26_EDGE_HIGH RW 0x0 10 GPIO26_EDGE_LOW RW 0x0 9 GPIO26_LEVEL_HIGH RW 0x0 8 GPIO26_LEVEL_LOW RW 0x0 7 GPIO25_EDGE_HIGH RW 0x0 6 GPIO25_EDGE_LOW RW 0x0 5 GPIO25_LEVEL_HIGH RW 0x0 4 GPIO25_LEVEL_LOW RW 0x0 3 GPIO24_EDGE_HIGH RW 0x0 2 GPIO24_EDGE_LOW RW 0x0 1 GPIO24_LEVEL_HIGH RW 0x0 0 GPIO24_LEVEL_LOW RW 0x0 T
RP2040 Datasheet Bits Name 16 Description Type Reset GPIO4_LEVEL_LOW RW 0x0 15 GPIO3_EDGE_HIGH RW 0x0 14 GPIO3_EDGE_LOW RW 0x0 13 GPIO3_LEVEL_HIGH RW 0x0 12 GPIO3_LEVEL_LOW RW 0x0 11 GPIO2_EDGE_HIGH RW 0x0 10 GPIO2_EDGE_LOW RW 0x0 9 GPIO2_LEVEL_HIGH RW 0x0 8 GPIO2_LEVEL_LOW RW 0x0 7 GPIO1_EDGE_HIGH RW 0x0 6 GPIO1_EDGE_LOW RW 0x0 5 GPIO1_LEVEL_HIGH RW 0x0 4 GPIO1_LEVEL_LOW RW 0x0 3 GPIO0_EDGE_HIGH RW 0x0 2 GPIO0_EDGE_LOW RW 0x0 1 GPIO0_LEVEL_
RP2040 Datasheet Bits Name 18 Description Type Reset GPIO12_EDGE_LOW RW 0x0 17 GPIO12_LEVEL_HIGH RW 0x0 16 GPIO12_LEVEL_LOW RW 0x0 15 GPIO11_EDGE_HIGH RW 0x0 14 GPIO11_EDGE_LOW RW 0x0 13 GPIO11_LEVEL_HIGH RW 0x0 12 GPIO11_LEVEL_LOW RW 0x0 11 GPIO10_EDGE_HIGH RW 0x0 10 GPIO10_EDGE_LOW RW 0x0 9 GPIO10_LEVEL_HIGH RW 0x0 8 GPIO10_LEVEL_LOW RW 0x0 7 GPIO9_EDGE_HIGH RW 0x0 6 GPIO9_EDGE_LOW RW 0x0 5 GPIO9_LEVEL_HIGH RW 0x0 4 GPIO9_LEVEL_LOW RW 0x0 3
RP2040 Datasheet Bits Name 20 Description Type Reset GPIO21_LEVEL_LOW RW 0x0 19 GPIO20_EDGE_HIGH RW 0x0 18 GPIO20_EDGE_LOW RW 0x0 17 GPIO20_LEVEL_HIGH RW 0x0 16 GPIO20_LEVEL_LOW RW 0x0 15 GPIO19_EDGE_HIGH RW 0x0 14 GPIO19_EDGE_LOW RW 0x0 13 GPIO19_LEVEL_HIGH RW 0x0 12 GPIO19_LEVEL_LOW RW 0x0 11 GPIO18_EDGE_HIGH RW 0x0 10 GPIO18_EDGE_LOW RW 0x0 9 GPIO18_LEVEL_HIGH RW 0x0 8 GPIO18_LEVEL_LOW RW 0x0 7 GPIO17_EDGE_HIGH RW 0x0 6 GPIO17_EDGE_LOW RW 0
RP2040 Datasheet Bits Name 15 Description Type Reset GPIO27_EDGE_HIGH RW 0x0 14 GPIO27_EDGE_LOW RW 0x0 13 GPIO27_LEVEL_HIGH RW 0x0 12 GPIO27_LEVEL_LOW RW 0x0 11 GPIO26_EDGE_HIGH RW 0x0 10 GPIO26_EDGE_LOW RW 0x0 9 GPIO26_LEVEL_HIGH RW 0x0 8 GPIO26_LEVEL_LOW RW 0x0 7 GPIO25_EDGE_HIGH RW 0x0 6 GPIO25_EDGE_LOW RW 0x0 5 GPIO25_LEVEL_HIGH RW 0x0 4 GPIO25_LEVEL_LOW RW 0x0 3 GPIO24_EDGE_HIGH RW 0x0 2 GPIO24_EDGE_LOW RW 0x0 1 GPIO24_LEVEL_HIGH RW 0x0
RP2040 Datasheet Bits Name 17 Description Type Reset GPIO4_LEVEL_HIGH RO 0x0 16 GPIO4_LEVEL_LOW RO 0x0 15 GPIO3_EDGE_HIGH RO 0x0 14 GPIO3_EDGE_LOW RO 0x0 13 GPIO3_LEVEL_HIGH RO 0x0 12 GPIO3_LEVEL_LOW RO 0x0 11 GPIO2_EDGE_HIGH RO 0x0 10 GPIO2_EDGE_LOW RO 0x0 9 GPIO2_LEVEL_HIGH RO 0x0 8 GPIO2_LEVEL_LOW RO 0x0 7 GPIO1_EDGE_HIGH RO 0x0 6 GPIO1_EDGE_LOW RO 0x0 5 GPIO1_LEVEL_HIGH RO 0x0 4 GPIO1_LEVEL_LOW RO 0x0 3 GPIO0_EDGE_HIGH RO 0x0 2 GPIO0_EDG
RP2040 Datasheet Bits Name 19 Description Type Reset GPIO12_EDGE_HIGH RO 0x0 18 GPIO12_EDGE_LOW RO 0x0 17 GPIO12_LEVEL_HIGH RO 0x0 16 GPIO12_LEVEL_LOW RO 0x0 15 GPIO11_EDGE_HIGH RO 0x0 14 GPIO11_EDGE_LOW RO 0x0 13 GPIO11_LEVEL_HIGH RO 0x0 12 GPIO11_LEVEL_LOW RO 0x0 11 GPIO10_EDGE_HIGH RO 0x0 10 GPIO10_EDGE_LOW RO 0x0 9 GPIO10_LEVEL_HIGH RO 0x0 8 GPIO10_LEVEL_LOW RO 0x0 7 GPIO9_EDGE_HIGH RO 0x0 6 GPIO9_EDGE_LOW RO 0x0 5 GPIO9_LEVEL_HIGH RO 0x0
RP2040 Datasheet Bits Name 21 Description Type Reset GPIO21_LEVEL_HIGH RO 0x0 20 GPIO21_LEVEL_LOW RO 0x0 19 GPIO20_EDGE_HIGH RO 0x0 18 GPIO20_EDGE_LOW RO 0x0 17 GPIO20_LEVEL_HIGH RO 0x0 16 GPIO20_LEVEL_LOW RO 0x0 15 GPIO19_EDGE_HIGH RO 0x0 14 GPIO19_EDGE_LOW RO 0x0 13 GPIO19_LEVEL_HIGH RO 0x0 12 GPIO19_LEVEL_LOW RO 0x0 11 GPIO18_EDGE_HIGH RO 0x0 10 GPIO18_EDGE_LOW RO 0x0 9 GPIO18_LEVEL_HIGH RO 0x0 8 GPIO18_LEVEL_LOW RO 0x0 7 GPIO17_EDGE_HIGH RO
RP2040 Datasheet Bits Name 16 Description Type Reset GPIO28_LEVEL_LOW RO 0x0 15 GPIO27_EDGE_HIGH RO 0x0 14 GPIO27_EDGE_LOW RO 0x0 13 GPIO27_LEVEL_HIGH RO 0x0 12 GPIO27_LEVEL_LOW RO 0x0 11 GPIO26_EDGE_HIGH RO 0x0 10 GPIO26_EDGE_LOW RO 0x0 9 GPIO26_LEVEL_HIGH RO 0x0 8 GPIO26_LEVEL_LOW RO 0x0 7 GPIO25_EDGE_HIGH RO 0x0 6 GPIO25_EDGE_LOW RO 0x0 5 GPIO25_LEVEL_HIGH RO 0x0 4 GPIO25_LEVEL_LOW RO 0x0 3 GPIO24_EDGE_HIGH RO 0x0 2 GPIO24_EDGE_LOW RO 0x0
RP2040 Datasheet Offset Name Info 0x38 PROC0_INTF Interrupt Force for proc0 0x3c PROC0_INTS Interrupt status after masking & forcing for proc0 0x40 PROC1_INTE Interrupt Enable for proc1 0x44 PROC1_INTF Interrupt Force for proc1 0x48 PROC1_INTS Interrupt status after masking & forcing for proc1 0x4c DORMANT_WAKE_INTE Interrupt Enable for dormant_wake 0x50 DORMANT_WAKE_INTF Interrupt Force for dormant_wake 0x54 DORMANT_WAKE_INTS Interrupt status after masking & forcing for dormant_w
RP2040 Datasheet Description GPIO control including function select and overrides. Table 338. GPIO_QSPI_SCLK_CTR L, GPIO_QSPI_SS_CTRL, …, GPIO_QSPI_SD2_CTRL, Bits Name Description Type Reset 31:30 Reserved. - - - 29:28 IRQOVER 0x0 → don’t invert the interrupt RW 0x0 GPIO_QSPI_SD3_CTRL 0x1 → invert the interrupt Registers 0x2 → drive interrupt low 0x3 → drive interrupt high 27:18 Reserved.
RP2040 Datasheet Bits Name 17 Description Type Reset GPIO_QSPI_SD2_LEVEL_HIGH RO 0x0 16 GPIO_QSPI_SD2_LEVEL_LOW RO 0x0 15 GPIO_QSPI_SD1_EDGE_HIGH WC 0x0 14 GPIO_QSPI_SD1_EDGE_LOW WC 0x0 13 GPIO_QSPI_SD1_LEVEL_HIGH RO 0x0 12 GPIO_QSPI_SD1_LEVEL_LOW RO 0x0 11 GPIO_QSPI_SD0_EDGE_HIGH WC 0x0 10 GPIO_QSPI_SD0_EDGE_LOW WC 0x0 9 GPIO_QSPI_SD0_LEVEL_HIGH RO 0x0 8 GPIO_QSPI_SD0_LEVEL_LOW RO 0x0 7 GPIO_QSPI_SS_EDGE_HIGH WC 0x0 6 GPIO_QSPI_SS_EDGE_LOW WC 0x0 5 GPI
RP2040 Datasheet Bits Name 12 Description Type Reset GPIO_QSPI_SD1_LEVEL_LOW RW 0x0 11 GPIO_QSPI_SD0_EDGE_HIGH RW 0x0 10 GPIO_QSPI_SD0_EDGE_LOW RW 0x0 9 GPIO_QSPI_SD0_LEVEL_HIGH RW 0x0 8 GPIO_QSPI_SD0_LEVEL_LOW RW 0x0 7 GPIO_QSPI_SS_EDGE_HIGH RW 0x0 6 GPIO_QSPI_SS_EDGE_LOW RW 0x0 5 GPIO_QSPI_SS_LEVEL_HIGH RW 0x0 4 GPIO_QSPI_SS_LEVEL_LOW RW 0x0 3 GPIO_QSPI_SCLK_EDGE_HIGH RW 0x0 2 GPIO_QSPI_SCLK_EDGE_LOW RW 0x0 1 GPIO_QSPI_SCLK_LEVEL_HIGH RW 0x0 0 GPIO_QS
RP2040 Datasheet Bits Name 7 Description Type Reset GPIO_QSPI_SS_EDGE_HIGH RW 0x0 6 GPIO_QSPI_SS_EDGE_LOW RW 0x0 5 GPIO_QSPI_SS_LEVEL_HIGH RW 0x0 4 GPIO_QSPI_SS_LEVEL_LOW RW 0x0 3 GPIO_QSPI_SCLK_EDGE_HIGH RW 0x0 2 GPIO_QSPI_SCLK_EDGE_LOW RW 0x0 1 GPIO_QSPI_SCLK_LEVEL_HIGH RW 0x0 0 GPIO_QSPI_SCLK_LEVEL_LOW RW 0x0 IO_QSPI: PROC0_INTS Register Offset: 0x3c Description Interrupt status after masking & forcing for proc0 Table 342. PROC0_INTS Register 2.19.
RP2040 Datasheet Bits Name 2 Description Type Reset GPIO_QSPI_SCLK_EDGE_LOW RO 0x0 1 GPIO_QSPI_SCLK_LEVEL_HIGH RO 0x0 0 GPIO_QSPI_SCLK_LEVEL_LOW RO 0x0 IO_QSPI: PROC1_INTE Register Offset: 0x40 Description Interrupt Enable for proc1 Table 343. PROC1_INTE Register Bits Name Description Type Reset 31:24 Reserved.
RP2040 Datasheet Description Interrupt Force for proc1 Table 344. PROC1_INTF Register Bits Name Description Type Reset 31:24 Reserved.
RP2040 Datasheet Bits Name 21 Description Type Reset GPIO_QSPI_SD3_LEVEL_HIGH RO 0x0 20 GPIO_QSPI_SD3_LEVEL_LOW RO 0x0 19 GPIO_QSPI_SD2_EDGE_HIGH RO 0x0 18 GPIO_QSPI_SD2_EDGE_LOW RO 0x0 17 GPIO_QSPI_SD2_LEVEL_HIGH RO 0x0 16 GPIO_QSPI_SD2_LEVEL_LOW RO 0x0 15 GPIO_QSPI_SD1_EDGE_HIGH RO 0x0 14 GPIO_QSPI_SD1_EDGE_LOW RO 0x0 13 GPIO_QSPI_SD1_LEVEL_HIGH RO 0x0 12 GPIO_QSPI_SD1_LEVEL_LOW RO 0x0 11 GPIO_QSPI_SD0_EDGE_HIGH RO 0x0 10 GPIO_QSPI_SD0_EDGE_LOW RO 0x0
RP2040 Datasheet Bits Name 16 Description Type Reset GPIO_QSPI_SD2_LEVEL_LOW RW 0x0 15 GPIO_QSPI_SD1_EDGE_HIGH RW 0x0 14 GPIO_QSPI_SD1_EDGE_LOW RW 0x0 13 GPIO_QSPI_SD1_LEVEL_HIGH RW 0x0 12 GPIO_QSPI_SD1_LEVEL_LOW RW 0x0 11 GPIO_QSPI_SD0_EDGE_HIGH RW 0x0 10 GPIO_QSPI_SD0_EDGE_LOW RW 0x0 9 GPIO_QSPI_SD0_LEVEL_HIGH RW 0x0 8 GPIO_QSPI_SD0_LEVEL_LOW RW 0x0 7 GPIO_QSPI_SS_EDGE_HIGH RW 0x0 6 GPIO_QSPI_SS_EDGE_LOW RW 0x0 5 GPIO_QSPI_SS_LEVEL_HIGH RW 0x0 4 GPIO_
RP2040 Datasheet Bits Name 11 Description Type Reset GPIO_QSPI_SD0_EDGE_HIGH RW 0x0 10 GPIO_QSPI_SD0_EDGE_LOW RW 0x0 9 GPIO_QSPI_SD0_LEVEL_HIGH RW 0x0 8 GPIO_QSPI_SD0_LEVEL_LOW RW 0x0 7 GPIO_QSPI_SS_EDGE_HIGH RW 0x0 6 GPIO_QSPI_SS_EDGE_LOW RW 0x0 5 GPIO_QSPI_SS_LEVEL_HIGH RW 0x0 4 GPIO_QSPI_SS_LEVEL_LOW RW 0x0 3 GPIO_QSPI_SCLK_EDGE_HIGH RW 0x0 2 GPIO_QSPI_SCLK_EDGE_LOW RW 0x0 1 GPIO_QSPI_SCLK_LEVEL_HIGH RW 0x0 0 GPIO_QSPI_SCLK_LEVEL_LOW RW 0x0 IO_QSPI: D
RP2040 Datasheet Bits Name 6 Description Type Reset GPIO_QSPI_SS_EDGE_LOW RO 0x0 5 GPIO_QSPI_SS_LEVEL_HIGH RO 0x0 4 GPIO_QSPI_SS_LEVEL_LOW RO 0x0 3 GPIO_QSPI_SCLK_EDGE_HIGH RO 0x0 2 GPIO_QSPI_SCLK_EDGE_LOW RO 0x0 1 GPIO_QSPI_SCLK_LEVEL_HIGH RO 0x0 0 GPIO_QSPI_SCLK_LEVEL_LOW RO 0x0 2.19.6.3. Pad Control - User Bank The User Bank Pad Control registers start at a base address of 0x4001c000 (defined as PADS_BANK0_BASE in SDK). Table 349. List of PADS_BANK0 registers 2.19.
RP2040 Datasheet Offset Name Info 0x60 GPIO23 Pad control register 0x64 GPIO24 Pad control register 0x68 GPIO25 Pad control register 0x6c GPIO26 Pad control register 0x70 GPIO27 Pad control register 0x74 GPIO28 Pad control register 0x78 GPIO29 Pad control register 0x7c SWCLK Pad control register 0x80 SWD Pad control register PADS_BANK0: VOLTAGE_SELECT Register Offset: 0x00 Table 350. VOLTAGE_SELECT Register Bits Description Type Reset 31:1 Reserved.
RP2040 Datasheet Description Pad control register Table 352. SWCLK Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 OD Output disable. Has priority over output enable from RW 0x1 peripherals 6 IE Input enable RW 0x1 5:4 DRIVE Drive strength. RW 0x1 0x0 → 2mA 0x1 → 4mA 0x2 → 8mA 0x3 → 12mA 3 PUE Pull up enable RW 0x1 2 PDE Pull down enable RW 0x0 1 SCHMITT Enable schmitt trigger RW 0x1 0 SLEWFAST Slew rate control.
RP2040 Datasheet Offset Name Info 0x04 GPIO_QSPI_SCLK Pad control register 0x08 GPIO_QSPI_SD0 Pad control register 0x0c GPIO_QSPI_SD1 Pad control register 0x10 GPIO_QSPI_SD2 Pad control register 0x14 GPIO_QSPI_SD3 Pad control register 0x18 GPIO_QSPI_SS Pad control register PADS_QSPI: VOLTAGE_SELECT Register Offset: 0x00 Table 355. VOLTAGE_SELECT Register Bits Description Type Reset 31:1 Reserved. - - 0 Voltage select. Per bank control RW 0x0 0x0 → Set voltage to 3.
RP2040 Datasheet Table 357. GPIO_QSPI_SD0, GPIO_QSPI_SD1, GPIO_QSPI_SD2, GPIO_QSPI_SD3 Registers Bits Name Description Type Reset 31:8 Reserved. - - - 7 OD Output disable. Has priority over output enable from RW 0x0 peripherals 6 IE Input enable RW 0x1 5:4 DRIVE Drive strength. RW 0x1 0x0 → 2mA 0x1 → 4mA 0x2 → 8mA 0x3 → 12mA 3 PUE Pull up enable RW 0x0 2 PDE Pull down enable RW 0x0 1 SCHMITT Enable schmitt trigger RW 0x1 0 SLEWFAST Slew rate control.
RP2040 Datasheet 2.20.2. List of Registers The sysinfo registers start at a base address of 0x40000000 (defined as SYSINFO_BASE in SDK). Table 359. List of SYSINFO registers Offset Name Info 0x00 CHIP_ID JEDEC JEP-106 compliant chip identifier. 0x04 PLATFORM Platform register. Allows software to know what environment it is running in. 0x40 GITREF_RP2040 Git hash of the chip source. Used to identify chip version.
RP2040 Datasheet ◦ DAP Instance ID (to change the address that the SWD uses to communicate with the core in debug) ◦ Processor status (If the processor is halted, which may be useful in debug) • Processor IO config ◦ Input synchroniser control (to allow input synchronisers to be bypassed to reduce latency where clocks are synchronous) • Debug control ◦ Provides the ability to control the SWD interface from inside the chip. This means Core 0 could debug Core 1, which may make debug connectivity easier.
RP2040 Datasheet Table 364. PROC0_NMI_MASK Register Bits Description Type Reset 31:0 Set a bit high to enable NMI from that IRQ RW 0x00000000 SYSCFG: PROC1_NMI_MASK Register Offset: 0x04 Description Processor core 1 NMI source mask Table 365. PROC1_NMI_MASK Register Bits Description Type Reset 31:0 Set a bit high to enable NMI from that IRQ RW 0x00000000 Type Reset RW 0x1 RW 0x0 SYSCFG: PROC_CONFIG Register Offset: 0x08 Description Configuration for processors Table 366.
RP2040 Datasheet Table 368. PROC_IN_SYNC_BYPA SS_HI Register Bits Description Type Reset 31:6 Reserved. - - 5:0 For each bit, if 1, bypass the input synchronizer between that GPIO RW 0x00 and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you’re feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30…35 (the QSPI IOs).
RP2040 Datasheet Bits Name 2 Description Type Reset SRAM2 RW 0x0 1 SRAM1 RW 0x0 0 SRAM0 RW 0x0 2.22. TBMAN TBMAN refers to the testbench manager, which is used during chip development simulations to verify the design. During these simulations TBMAN allows software running on RP2040 to control the testbench and simulation environment. On the real chip it has no effect other than providing a single PLATFORM register to indicate that this is the real chip.
RP2040 Datasheet Chapter 3. PIO 3.1. Overview There are 2 identical PIO blocks in RP2040. Each PIO block has dedicated connections to the bus fabric, GPIO and interrupt controller. The diagram for a single PIO block is show in Figure 38. Figure 38. PIO blocklevel diagram. There are two PIO blocks with four state machines each. The four state machines simultaneously execute programs from a shared instruction memory. FIFO data queues buffer data transferred between PIO and the system.
RP2040 Datasheet • Flexible GPIO mapping • DMA interface, sustained throughput up to 1 word per clock from system DMA • IRQ flag set/clear/status Each state machine, along with its supporting hardware, occupies approximately the same silicon area as a standard serial interface block, such as an SPI or I2C controller. However, PIO state machines can be configured and reconfigured dynamically to implement numerous different interfaces.
RP2040 Datasheet The PIO has a total of nine instructions: JMP, WAIT, IN, OUT, PUSH, PULL, MOV, IRQ, and SET. See Section 3.4 for details on these instructions. Though the PIO only has a total of nine instructions, it would be difficult to edit PIO program binaries by hand. PIO assembly is a textual format, describing a PIO program, where each command corresponds to one instruction in the output binary. Below is an example program in PIO assembly: Pico Examples: https://github.
RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/squarewave/squarewave.c Lines 42 - 47 42 // Configure state machine 0 to run at sysclk/2.5. The state machines can 43 // run as fast as one instruction per clock cycle, but we can scale their 44 // speed down uniformly to meet some precise frequency target, e.g. for a 45 // UART baud rate. This register has 16 integer divisor bits and 8 46 // fractional divisor bits. 47 pio->sm[0].
RP2040 Datasheet 3.2.3.1. Output Shift Register (OSR) Figure 40. Output Shift Register (OSR). Data is parcelled out 1…32 bits at a time, and unused data is recycled by a bidirectional shifter. Once empty, the OSR is reloaded from the TX FIFO. The Output Shift Register (OSR) holds and shifts output data, between the TX FIFO and the pins (or other destinations, such as the scratch registers). • PULL instructions: remove a 32-bit word from the TX FIFO and place into the OSR.
RP2040 Datasheet 6 .wrap 3.2.3.2. Input Shift Register (ISR) Figure 41. Input Shift Register (ISR). Data enters 1…32 bits at a time, and current contents is shifted left or right to make room. Once full, contents is written to the RX FIFO. • IN instructions shift 1…32 bits at a time into the register. • PUSH instructions write the ISR contents to the RX FIFO. • The ISR is cleared to all-zeroes when pushed.
RP2040 Datasheet For example, suppose we wanted to produce a long pulse for "1" data bits, and a short pulse for "0" data bits: 1 .
RP2040 Datasheet NOTE Side-set (Section 3.5.1) is not affected by stalls, and always takes place on the first cycle of the attached instruction. 3.2.5. Pin Mapping PIO controls the output level and direction of up to 32 GPIOs, and can observe their input levels.
RP2040 Datasheet 3.3. PIO Assembler (pioasm) The PIO Assembler parses a PIO source file and outputs the assembled version ready for inclusion in an RP2040 application. This includes C and C++ applications built against the SDK, and Python programs running on the RP2040 MicroPython port. This section briefly introduces the directives and instructions that can be used in pioasm input.
RP2040 Datasheet 3.3.2. Values The following types of values can be used to define integer numbers or branch targets Table 374. Values in pioasm, i.e. integer An integer value e.g. 3 or -7 hex A hexadecimal value e.g. 0xf binary A binary value e.g. 0b1001 symbol A value defined by a .define (see [pioasm_define])
RP2040 Datasheet TIP A label is really just an automatic .define with a value set to the current program instruction offset. A PUBLIC label is exposed to the user code in the same way as a PUBLIC .define. 3.3.6. Instructions All pioasm instructions follow a common pattern: (side ) ([]) where: Is an assembly instruction detailed in the following sections. (See Section 3.4) Is a value (see Section 3.3.
RP2040 Datasheet Table 376.
RP2040 Datasheet JMP PIN branches on the GPIO selected by EXECCTRL_JMP_PIN, a configuration field which selects one out of the maximum of 32 GPIO inputs visible to a state machine, independently of the state machine’s other input mapping. The branch is taken if the GPIO is high. !OSRE compares the bits shifted out since the last PULL with the shift count threshold configured by SHIFTCTRL_PULL_THRESH. This is the same threshold used by autopull (Section 3.5.4).
RP2040 Datasheet ◦ 11: Reserved • Index: which pin or bit to check. WAIT x IRQ behaves slightly differently from other WAIT sources: • If Polarity is 1, the selected IRQ flag is cleared by the state machine upon the wait condition being met. • The flag index is decoded in the same way as the IRQ index field: if the MSB is set, the state machine ID (0…3) is added to the IRQ index, by way of modulo-4 addition on the two LSBs.
RP2040 Datasheet ◦ 001: X (scratch register X) ◦ 010: Y (scratch register Y) ◦ 011: NULL (all zeroes) ◦ 100: Reserved ◦ 101: Reserved ◦ 110: ISR ◦ 111: OSR • Bit count: How many bits to shift into the ISR. 1…32 bits, 32 is encoded as 00000. If automatic push is enabled, IN will also push the ISR contents to the RX FIFO if the push threshold is reached (SHIFTCTRL_PUSH_THRESH). IN still executes in one cycle, whether an automatic push takes place or not.
RP2040 Datasheet ◦ 010: Y (scratch register Y) ◦ 011: NULL (discard data) ◦ 100: PINDIRS ◦ 101: PC ◦ 110: ISR (also sets ISR shift counter to Bit count) ◦ 111: EXEC (Execute OSR shift data as instruction) • Bit count: how many bits to shift out of the OSR. 1…32 bits, 32 is encoded as 00000. A 32-bit value is written to Destination: the lower Bit count bits come from the OSR, and the remainder are zeroes.
RP2040 Datasheet point. The PIO assembler sets the Block bit by default. If the Block bit is not set, the PUSH does not stall on a full RX FIFO, instead continuing immediately to the next instruction. The FIFO state and contents are unchanged when this happens. The ISR is still cleared to all-zeroes, and the FDEBUG_RXSTALL flag is set (the same as a blocking PUSH or autopush to a full RX FIFO) to indicate data was lost. 3.4.6.3.
RP2040 Datasheet NOTE When autopull is enabled, any PULL instruction is a no-op when the OSR is full, so that the PULL instruction behaves as a barrier. OUT NULL, 32 can be used to explicitly discard the OSR contents. See Section 3.5.4.2 for more detail. 3.4.7.3. Assembler Syntax pull ( ifempty ) pull ( ifempty ) block pull ( ifempty ) noblock where: ifempty Is equivalent to IfEmpty == 1 above. i.e. the default if this is not specified is IfEmpty == 0 block Is equivalent to Block == 1 above.
RP2040 Datasheet • Source: ◦ 000: PINS (Uses same pin mapping as IN) ◦ 001: X ◦ 010: Y ◦ 011: NULL ◦ 100: Reserved ◦ 101: STATUS ◦ 110: ISR ◦ 111: OSR MOV PC causes an unconditional jump. MOV EXEC has the same behaviour as OUT EXEC (Section 3.4.5), and allows register contents to be executed as an instruction. The MOV itself executes in 1 cycle, and the instruction in Source on the next cycle. Delay cycles on MOV EXEC are ignored, but the executee may insert delay cycles as normal.
RP2040 Datasheet • Index: ◦ The 3 LSBs specify an IRQ index from 0-7. This IRQ flag will be set/cleared depending on the Clear bit. ◦ If the MSB is set, the state machine ID (0…3) is added to the IRQ index, by way of modulo-4 addition on the two LSBs. For example, state machine 2 with a flag value of 0x11 will raise flag 3, and a flag value of 0x13 will raise flag 1.
RP2040 Datasheet • 001: X (scratch register X) 5 LSBs are set to Data, all others cleared to 0. • 010: Y (scratch register Y) 5 LSBs are set to Data, all others cleared to 0. • 011: Reserved • 100: PINDIRS • 101: Reserved • 110: Reserved • 111: Reserved • Data: 5-bit immediate value to drive to pins or register. This can be used to assert control signals such as a clock or chip select, or to initialise loop counters.
RP2040 Datasheet The side-set data is encoded in the Delay/side-set field of each instruction. Any instruction can be combined with sideset, including instructions which write to the pins, such as OUT PINS or SET PINS. Side-set’s pin mapping is independent from OUT and SET mappings, though it may overlap. If side-set and an OUT or SET write to the same pin simultaneously, the side-set data is used. NOTE If an instruction stalls, the side-set still takes effect immediately. 1 .program spi_tx_fast 2 .
RP2040 Datasheet • The JMP takes up space in the instruction memory that could be used for other programs • The extra cycle taken to execute the JMP ends up halving the maximum output rate As the Program Counter (PC) naturally wraps to 0 when incremented past 31, we could solve the second of these by filling the entire instruction memory with a repeating pattern of set pins, 1 and set pins, 0, but this is wasteful.
RP2040 Datasheet 31 static inline pio_sm_config squarewave_wrap_program_get_default_config(uint offset) { 32 pio_sm_config c = pio_get_default_sm_config(); 33 sm_config_set_wrap(&c, offset + squarewave_wrap_wrap_target, offset + squarewave_wrap_wrap); 34 return c; 35 } 36 #endif This is raw output from the PIO assembler, pioasm, which has created a default pio_sm_config object containing the WRAP register values from the program listing.
RP2040 Datasheet implemented on two separate state machines. It would be wasteful to leave half of each state machine’s FIFO resources idle. The ability to join the two halves into just a TX FIFO for the TX/CTS state machine, or just an RX FIFO in the case of the RX/RTS state machine, allows full utilisation. A UART equipped with an 8-deep FIFO can be left alone for twice as long between interrupts as one with only a 4-deep FIFO.
RP2040 Datasheet Figure 43. Execution of manual_pull System Clock program. X is used as Instruction a loop counter. On and the clock is PULL OUT JMP 2 Scratch X each iteration, one data bit is shifted out, SET OUT JMP 1 Data pin (OUT) OUT JMP OUT 0 SET PULL -1 2 Bit 0 Bit 1 Bit 2 Bit 3 1 2 3 4 Clock pin (side -set) asserted low, then high. A delay cycle on each instruction OSR shift count 32 0 brings the total up to four cycles per iteration.
RP2040 Datasheet 1 .program auto_push_pull 2 3 .wrap_target 4 out x, 32 5 in x, 32 6 .wrap 1 #include "tb.h" // TODO this is built against existing sw tree, so that we get printf etc 2 3 #include "platform.h" 4 #include "pio_regs.h" 5 #include "system.h" 6 #include "hardware.h" 7 8 #include "auto_push_pull.pio.h" 9 10 int main() 11 { 12 tb_init(); 13 14 // Load program and configure state machine 0 for autopush/pull with 15 // threshold of 32, and wrapping on program boundary.
RP2040 Datasheet Figure 44. Execution of auto_push_pull program. The state clock OUT Current Instruction machine stalls on an IN OUT IN OUT IN OUT IN OUT IN OUT Stall OUT until data has travelled through the TX FIFO into the OSR.
RP2040 Datasheet 1 if MOV or PULL: 2 osr count = 0 3 4 if osr count >= threshold: 5 if tx fifo not empty: 6 osr = pull() 7 osr count = 0 An autopull can therefore occur at any point between two 'OUT' s, depending on when the data arrives in the FIFO.
RP2040 Datasheet that the state machine runs at some steady pace, potentially much slower than the system clock. Implementing the clock dividers in this way allows interfacing between the state machines and the system to be simpler, lower-latency, and with a smaller footprint. The state machine is completely idle on cycles where clock enable is low, though the system can still access the state machine’s FIFOs and change its configuration.
RP2040 Datasheet Figure 48. The state machine has two independent output channels, one shared by OUT/SET, and another used by sideset (which can happen at any time). Three independent mappings (first GPIO, number of GPIOs) control which GPIOs OUT, SET and side-set are directed to. Input data is rotated according to which GPIO is mapped to the LSB of the IN data.
RP2040 Datasheet Figure 49. Per-GPIO priority select of write masks from each state machine. Each GPIO considers level and direction writes from each of the four state machines, and applies the value from the highest-numbered state machine. Each state machine may assert an OUT/SET and a side-set through its pin mapping hardware on each cycle. This generates 32 bits of write data and write mask for the GPIO output level and output enable registers, from each state machine.
RP2040 Datasheet • MOV EXEC which executes an instruction from some register Source • OUT EXEC which executes data shifted out from the OSR • The SMx_INSTR control registers, to which the system can write instructions for immediate execution 1 .program exec_example 2 3 hang: 4 jmp hang 5 execute: 6 out exec, 32 7 jmp execute 8 9 .program instructions_to_push 10 11 out x, 32 12 in x, 32 13 push 1 #include "tb.
RP2040 Datasheet Here we load an example program into the state machine, which does two things: • Enters an infinite loop • Enters a loop which repeatedly pulls 32 bits of data from the TX FIFO, and executes the lower 16 bits as an instruction The C program sets the state machine running, at which point it enters the hang loop. While the state machine is still running, the C program forces in a jmp instruction, which causes the state machine to break out of the loop.
RP2040 Datasheet Figure 50. In SPI, a host and device exchange data over a bidirectional pair of serial data lines, synchronous with a clock (SCK). Two flags, CPOL and CPHA, specify the clock’s behaviour. CPOL is the idle state of the clock: 0 for low, 1 for high. The clock pulses a number of times, transferring one bit in each direction per pulse, but always SPI is a common serial interface with a twisty history. The following program implements full-duplex (i.e.
RP2040 Datasheet NOTE These programs do not control the chip select line; chip select is often implemented as a software-controlled GPIO, due to wildly different behaviour between different SPI hardware. The full spi.pio source linked above contains some examples how PIO can implement a hardware chip select line. A C helper function configures the state machine, connects the GPIOs, and sets the state machine running.
RP2040 Datasheet 28 } 29 if (rx_remain && !pio_sm_is_rx_fifo_empty(spi->pio, spi->sm)) { 30 (void) *rxfifo; 31 --rx_remain; 32 } 33 } 34 } Putting this all together, this complete C program will loop back some data through a PIO SPI at 1 MHz, with all four CPOL/CPHA combinations: Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/spi/spi_loopback.c Lines 1 - 77 1 /** 2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
RP2040 Datasheet 50 stdio_init_all(); 51 52 pio_spi_inst_t spi = { 53 .pio = pio0, 54 .sm = 0 55 }; 56 float clkdiv = 31.25f; 57 uint cpha0_prog_offs = pio_add_program(spi.pio, &spi_cpha0_program); 58 uint cpha1_prog_offs = pio_add_program(spi.pio, &spi_cpha1_program); // 1 MHz @ 125 clk_sys 59 60 for (int cpha = 0; cpha <= 1; ++cpha) { 61 for (int cpol = 0; cpol <= 1; ++cpol) { 62 printf("CPHA = %d, CPOL = %d\n", cpha, cpol); 63 pio_spi_init(spi.pio, spi.
RP2040 Datasheet 21 jmp !x do_zero side 1 [T1 - 1] ; Branch on the bit we shifted out. Positive pulse 22 do_one: 23 jmp bitloop side 1 [T2 - 1] ; Continue driving high, for a long pulse 24 do_zero: 25 nop side 0 [T2 - 1] ; Or drive low, for a short pulse 26 .wrap This program shifts bits from the OSR into X, and produces a wide or narrow pulse on side-set pin 0, based on the value of each data bit. Autopull must be configured, with a threshold of 24.
RP2040 Datasheet 3.6.3. UART TX Figure 52. UART serial Bit Clock format. The line is 0 TX high when idle. The transmitter pulls the State Idle 1 2 Start 3 4 5 6 7 Data (LSB first) Stop line down for one bit period to signify the start of a serial frame (the "start bit"), and a small, fixed number of This program implements the transmit component of a universal asynchronous receive/transmit (UART) serial peripheral. Perhaps it would be more correct to refer to this as a UAT.
RP2040 Datasheet 39 sm_config_set_sideset_pins(&c, pin_tx); 40 41 // We only need TX, so get an 8-deep FIFO! 42 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); 43 44 // SM transmits 1 bit per 8 execution cycles.
RP2040 Datasheet 25 26 sleep_ms(1000); } 27 } With the two PIO instances on RP2040, this could be extended to 8 additional UART TX interfaces, on 8 different pins, with 8 different baud rates. 3.6.4. UART RX Recalling Figure 52 showing the format of an 8n1 UART: Bit Clock 0 TX State Idle 1 2 Start 3 4 5 6 7 Data (LSB first) Stop We can recover the data by waiting for the start bit, sampling 8 times with the correct timing, and pushing the result to the RX FIFO.
RP2040 Datasheet 60 61 good_stop: ; No delay before returning to start; a little slack is 62 ; important in case the TX clock is slightly too fast. push The second example does not use autopush (Section 3.5.4), preferring instead to use an explicit push instruction, so that it can condition the push on whether a correct stop bit is seen. The .pio file includes a helper function which configures the state machine and connects it to a GPIO with the pullup enabled: Pico Examples: https://github.
RP2040 Datasheet 2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include 8 9 #include "pico/stdlib.h" 10 #include "pico/multicore.h" 11 #include "hardware/pio.h" 12 #include "hardware/uart.h" 13 #include "uart_rx.pio.
RP2040 Datasheet 3.6.5. Manchester Serial TX and RX Figure 53. Manchester serial line code. Each data bit is represented by either a high pulse followed by a low pulse (representing a '0' bit) or a low pulse Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/manchester_encoding/manchester_encoding.pio Lines 7 - 29 followed by a high pulse (a '1' bit). 7 .program manchester_tx 8 .side_set 1 opt 9 10 ; Transmit one bit every 12 cycles.
RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/manchester_encoding/manchester_encoding.pio Lines 48 - 70 48 .program manchester_rx 49 50 ; Assumes line is idle low, first bit is 0 51 ; One bit is 12 cycles 52 ; a '0' is encoded as 10 53 ; a '1' is encoded as 01 54 ; 55 ; Both the IN base and the JMP pin mapping must be pointed at the GPIO used for RX. 56 ; Autopush must be enabled.
RP2040 Datasheet The example C program in the SDK will transmit Manchester serial data from GPIO2 to GPIO3 at approximately 10 Mbps (assuming a system clock of 125 MHz). Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/manchester_encoding/manchester_encoding.
RP2040 Datasheet 19 out x, 1 20 jmp !x high_0 ; Start of bit period: always assert transition side 1 [6] ; Test the data bit we just shifted out of OSR 21 high_1: 22 nop 23 jmp initial_high side 0 [6] ; For `1` bits, also transition in the middle 24 high_0: 25 jmp initial_low [7] ; Otherwise, the line is stable in the middle 26 27 initial_low: 28 out x, 1 29 jmp !x low_0 ; Always shift 1 bit from OSR to X so we can side 0 [6] ; branch on it. Autopull refills OSR for us.
RP2040 Datasheet 60 ; 61 ; The IN mapping and the JMP pin select must both be mapped to the GPIO used for 62 ; RX data. Autopush must be enabled. 63 64 public start: 65 initial_high: 66 wait 1 pin, 0 67 jmp pin high_0 ; Find rising edge at start of bit period [11] ; Delay to eye of second half-period (i.e 3/4 of way ; through bit) and branch on RX pin high/low.
RP2040 Datasheet 7 #include 8 9 #include "pico/stdlib.h" 10 #include "hardware/pio.h" 11 #include "differential_manchester.pio.
RP2040 Datasheet Figure 55. A 1-byte I2C read transfer. In the idle state, both lines float high. The initiator drives SDA low (a Start condition), followed by 7 address bits A6-A0, and a I2C is an ubiquitous serial bus first described in the Dead Sea Scrolls, and later used by Philips Semiconductor. Two direction bit wires with pullup resistors form an open-drain bus, and multiple agents address and signal one another over this bus by (Read/nWrite).
RP2040 Datasheet 43 44 do_nack: 45 jmp y-- entry_point ; Continue if NAK was expected 46 irq wait 0 rel ; Otherwise stop, ask for help 47 48 do_byte: 49 set x, 7 ; Loop 8 times 50 bitloop: 51 out pindirs, 1 52 nop [7] ; Serialise write data (all-ones if reading) 53 wait 1 pin, 1 [4] ; Allow clock to be stretched 54 in pins, 1 [7] ; Sample read data in middle of SCL pulse 55 jmp x-- bitloop side 0 [7] ; SCL falling edge side 1 [2] ; SCL rising edge 56 57 ; Handle ACK pulse 58 out p
RP2040 Datasheet 101 gpio_pull_up(pin_sda); 102 uint32_t both_pins = (1u << pin_sda) | (1u << pin_scl); 103 pio_sm_set_pins_with_mask(pio, sm, both_pins, both_pins); 104 pio_sm_set_pindirs_with_mask(pio, sm, both_pins, both_pins); 105 pio_gpio_init(pio, pin_sda); 106 gpio_set_oeover(pin_sda, GPIO_OVERRIDE_INVERT); 107 pio_gpio_init(pio, pin_scl); 108 gpio_set_oeover(pin_scl, GPIO_OVERRIDE_INVERT); 109 pio_sm_set_pins_with_mask(pio, sm, 0, both_pins); 110 111 // Clear IRQ flag before star
RP2040 Datasheet 142 pio_i2c_resume_after_error(pio, sm); 143 pio_i2c_stop(pio, sm); 144 } Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/i2c/pio_i2c.c Lines 19 - 23 19 void pio_i2c_resume_after_error(PIO pio, uint sm) { 20 pio_sm_drain_tx_fifo(pio, sm); 21 pio_sm_exec(pio, sm, (pio->sm[sm].
RP2040 Datasheet Figure 56. Pulse width modulation (PWM). The state machine outputs positive voltage pulses at regular intervals. The width of these pulses is controlled, so that the line is high for This program repeatedly counts down to 0 with the Y register, whilst comparing the Y count to a pulse width held in the some controlled X register. The output is asserted low before counting begins, and asserted high when the value in Y reaches X. Once Y fraction of the time (the duty cycle).
RP2040 Datasheet 16 pio_sm_put_blocking(pio, sm, period); 17 pio_sm_exec(pio, sm, pio_encode_pull(false, false)); 18 pio_sm_exec(pio, sm, pio_encode_out(pio_isr, 32)); 19 pio_sm_set_enabled(pio, sm, true); 20 } Once this is done, the state machine can be enabled, and PWM values written directly to its TX FIFO. Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/pwm/pwm.
RP2040 Datasheet 6 ; 7 ; This program uses the two's complement identity x + y == ~(~x - y) 8 9 pull 10 mov x, ~osr 11 pull 12 mov y, osr 13 jmp test ; this loop is equivalent to the following C code: 14 incr: ; while (y--) 15 ; jmp x-- test 16 test: x--; ; This has the effect of subtracting y from x, eventually. 17 jmp y-- incr 18 mov isr, ~x 19 push A full 32-bit addition takes only around one minute at 125 MHz.
RP2040 Datasheet 3.6.10. Further Examples The Raspberry Pi Pico C/C++ SDK book has a PIO chapter which goes into depth on some software-centric topics not presented here. It includes a PIO + DMA logic analyser example that can sample every GPIO on every cycle (a bandwidth of nearly 4 Gb/s at 125 MHz, although this does fill up RP2040’s RAM quite quickly). There are also further examples in the pio/ directory in the Pico Examples repository.
RP2040 Datasheet Offset Name Info 0x028 RXF2 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. 0x02c RXF3 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO.
RP2040 Datasheet Offset Name Info 0x05c INSTR_MEM5 Write-only access to instruction memory location 5 0x060 INSTR_MEM6 Write-only access to instruction memory location 6 0x064 INSTR_MEM7 Write-only access to instruction memory location 7 0x068 INSTR_MEM8 Write-only access to instruction memory location 8 0x06c INSTR_MEM9 Write-only access to instruction memory location 9 0x070 INSTR_MEM10 Write-only access to instruction memory location 10 0x074 INSTR_MEM11 Write-only access to instr
RP2040 Datasheet Offset Name Info 0x0dc SM0_PINCTRL State machine pin control 0x0e0 SM1_CLKDIV Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 0x0e4 SM1_EXECCTRL Execution/behavioural settings for state machine 1 0x0e8 SM1_SHIFTCTRL Control behaviour of the input/output shift registers for state machine 1 0x0ec SM1_ADDR Current instruction address of state machine 1 0x0f0 SM1_INSTR Read to see the instruction currently addressed by st
RP2040 Datasheet PIO: CTRL Register Offset: 0x000 Description PIO control register Table 378. CTRL Register Bits Name Description Type Reset 31:12 Reserved. - - - 11:8 CLKDIV_RESTART Restart a state machine’s clock divider from an initial SC 0x0 SC 0x0 RW 0x0 phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV.
RP2040 Datasheet Bits Name Description Type Reset 27:24 TXEMPTY State machine TX FIFO is empty RO 0xf 23:20 Reserved. - - - 19:16 TXFULL State machine TX FIFO is full RO 0x0 15:12 Reserved. - - - 11:8 RXEMPTY State machine RX FIFO is empty RO 0xf 7:4 Reserved. - - - 3:0 RXFULL State machine RX FIFO is full RO 0x0 PIO: FDEBUG Register Offset: 0x008 Description FIFO debug register Table 380. FDEBUG Register Bits Name Description Type Reset 31:28 Reserved.
RP2040 Datasheet Table 381. FLEVEL Register Bits Name 31:28 Description Type Reset RX3 RO 0x0 27:24 TX3 RO 0x0 23:20 RX2 RO 0x0 19:16 TX2 RO 0x0 15:12 RX1 RO 0x0 11:8 TX1 RO 0x0 7:4 RX0 RO 0x0 3:0 TX0 RO 0x0 PIO: TXF0, TXF1, TXF2, TXF3 Registers Offsets: 0x010, 0x014, 0x018, 0x01c Table 382. TXF0, TXF1, TXF2, TXF3 Registers Bits Description Type Reset 31:0 Direct write access to the TX FIFO for this state machine.
RP2040 Datasheet Table 385. IRQ_FORCE Register Bits Description Type Reset 31:8 Reserved. - - 7:0 Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. WF 0x00 Type Reset Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. PIO: INPUT_SYNC_BYPASS Register Offset: 0x038 Table 386.
RP2040 Datasheet Bits Name Description Type Reset 11:8 SM_COUNT The number of state machines this PIO instance is RO - - - equipped with. 7:6 Reserved. - 5:0 FIFO_DEPTH The depth of the state machine TX/RX FIFOs, measured in RO - words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth. PIO: INSTR_MEM0, INSTR_MEM1, …, INSTR_MEM30, INSTR_MEM31 Registers Offsets: 0x048, 0x04c, …, 0x0c0, 0x0c4 Table 390.
RP2040 Datasheet Bits Name Description Type Reset 29 SIDE_PINDIR If 1, side-set data is asserted to pin directions, instead of RW 0x0 RW 0x00 pin values 28:24 JMP_PIN The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
RP2040 Datasheet Bits Name Description Type Reset 24:20 PUSH_THRESH Number of bits shifted into ISR before autopush, or RW 0x00 conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. 19 OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. RW 0x1 18 IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). RW 0x1 0 = to left. 17 AUTOPULL Pull automatically when the output shift register is RW 0x0 RW 0x0 - - emptied, i.e.
RP2040 Datasheet Bits Name Description Type Reset 25:20 OUT_COUNT The number of pins asserted by an OUT PINS, OUT RW 0x00 RW 0x00 RW 0x00 RW 0x00 RW 0x00 PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. 19:15 IN_BASE The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
RP2040 Datasheet Offset: 0x12c Description Interrupt Enable for irq0 Table 398. IRQ0_INTE Register Bits Name Description Type Reset 31:12 Reserved.
RP2040 Datasheet Offset: 0x134 Description Interrupt status after masking & forcing for irq0 Table 400. IRQ0_INTS Register Bits Name Description Type Reset 31:12 Reserved.
RP2040 Datasheet Offset: 0x13c Description Interrupt Force for irq1 Table 402. IRQ1_INTF Register Bits Name Description Type Reset 31:12 Reserved.
RP2040 Datasheet Chapter 4. Peripherals 4.1. USB 4.1.1. Overview Prerequisite Knowledge Required This section requires knowledge of the USB protocol. We recommend [usbmadesimple] if you are unclear on the terminology used in this section (see References). RP2040 contains a USB 2.0 controller that can operate as either: • a Full Speed device (12 Mbit/s) • a host that can communicate with both Low Speed (1.5 Mbit/s) and Full Speed devices. This includes multiple downstream devices connected to a USB hub.
RP2040 Datasheet 4.1.2. Architecture Figure 57. A simplified overview of the USB controller architecture. The USB controller is an area efficient design that muxes a device controller or host controller onto a common set of components. Each component is detailed below. 4.1.2.1. USB PHY The USB PHY provides the electrical interface between the USB DP and DM pins and the digital logic of the controller.
RP2040 Datasheet NOTE If you disconnect the USB cable during a packet in either host or device mode you will see errors raised by the hardware. Your software will need to take this scenario into account if you enable error interrupts. 4.1.2.4. Serial TX Engine The serial transmit engine is a mirror of the serial receive engine. It is connected to the currently active controller (either device or host). It creates TOKEN and DATA packets, including calculating the CRC, and transmits them on the bus. 4.1.
RP2040 Datasheet 4.1.
RP2040 Datasheet Offset Device Function Host Function 0xd0 EP10 in buffer control Interrupt endpoint buffer control 10 0xd4 EP10 out buffer control Spare 0xd8 EP11 in buffer control Interrupt endpoint buffer control 11 0xdc EP11 out buffer control Spare 0xe0 EP12 in buffer control Interrupt endpoint buffer control 12 0xe4 EP12 out buffer control Spare 0xe8 EP13 in buffer control Interrupt endpoint buffer control 13 0xec EP13 out buffer control Spare 0xf0 EP14 in buffer control
RP2040 Datasheet NOTE The data buffer base address must be 64-byte aligned as bits 0-5 are ignored 4.1.2.5.3. Buffer control register The buffer control register contains information about the state of the data buffers for that endpoint. It is shared between the processor and the controller. If the endpoint is configured to be single buffered, only the first half (bits 015) of the buffer are used. If double buffering, the buffer select starts at buffer 0.
RP2040 Datasheet 4.1.2.6.1. SETUP The device controller MUST always accept a setup packet from the host. That is why the first 8 bytes of the DPSRAM has dedicated space for the setup packet. The [usbspec] states that receiving a setup packet also clears any stall bits on EP0. For this reason, the stall bits for EP0 are gated with two bits in the EP_STALL_ARM register. These bits are cleared when a setup packet is received.
RP2040 Datasheet • Is the AVAILABLE bit set and the FULL bit unset. If so go to the data phase, unless the STALL bit is set in which case the device controller will reply with a STALL. DATA phase: • Store received data in buffer. If Isochronous go to STATUS phase. Otherwise go to ACK phase. ACK phase: • Send ACK. Go to STATUS phase. STATUS phase: See status phase from Section 4.1.2.6.2.
RP2040 Datasheet • PREAMBLE_ENABLE - Use this to send a packet to a Low Speed device on a Full Speed hub. This will send a PRE token packet before every packet the host sends (i.e. pre, token, pre, data, pre, ack). • SOF_SYNC - The SOF Sync bit is used to delay the transaction until after the next SOF. This is useful for interrupt and isochronous endpoints. The Host controller prevents a transaction of 64bytes from clashing with the SOF packets.
RP2040 Datasheet send a zero length packet to the host to indicate that it has no more data. In which case the host state machine will stop listening for more data regardless of if the LAST_BUFF flag was set or not. The host software can tell this has happened because BUFF_DONE will be set with a data length of 0 in the buffer control register.
RP2040 Datasheet • Program the appropriate endpoint control register and buffer control register like you would with a normal IN or OUT transfer. Note that interrupt endpoints are only single buffered so the BUF1 part of the buffer control register is invalid. • Set the address and endpoint of the device in the appropriate ADDR_ENDP register (ADDR_ENDP1 to ADDR_ENDP15). The preamble bit should be set if the device is Low Speed but attached to a Full Speed hub.
RP2040 Datasheet The code included in this section will walk you through setting up to the USB device controller to receive a setup packet, and then respond to the setup packet. Figure 58. USB analyser trace of the dev_lowlevel USB device example. The control transfers are the device enumeration. The first bulk OUT (out from the host) transfer, highlighted in blue, is the host sending "Hello World" to the device.
RP2040 Datasheet 213 // described by device configuration 214 usb_setup_endpoints(); 215 216 // Present full speed device by enabling pull up on DP 217 usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; 218 } 4.1.3.2.2.
RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/usb/device/dev_lowlevel/dev_lowlevel.
RP2040 Datasheet 272 ep->next_pid = 1; 273 usb_start_transfer(ep, (uint8_t *) d, sizeof(struct usb_device_descriptor)); 274 } The usb_start_transfer function copies the data to send into the appropriate hardware buffer, and configures the buffer control register. Once the buffer control register has been written to, the device controller will respond to the host with the data. Before this point, the device will reply with a NAK. Pico Examples: https://github.
RP2040 Datasheet Offset Name Info 0x28 ADDR_ENDP10 Interrupt endpoint 10. Only valid for HOST mode. 0x2c ADDR_ENDP11 Interrupt endpoint 11. Only valid for HOST mode. 0x30 ADDR_ENDP12 Interrupt endpoint 12. Only valid for HOST mode. 0x34 ADDR_ENDP13 Interrupt endpoint 13. Only valid for HOST mode. 0x38 ADDR_ENDP14 Interrupt endpoint 14. Only valid for HOST mode. 0x3c ADDR_ENDP15 Interrupt endpoint 15. Only valid for HOST mode.
RP2040 Datasheet Offset Name Info 0x78 USB_PWR Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. 0x7c USBPHY_DIRECT This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.
RP2040 Datasheet Bits Name Description Type Reset 6:0 ADDRESS Device address RW 0x00 USB: MAIN_CTRL Register Offset: 0x40 Description Main control register Table 410. MAIN_CTRL Register Bits Name Description Type Reset 31 SIM_TIMING Reduced timings for simulation RW 0x0 30:2 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 29 EP0_INT_1BUF Device: Set bit in BUFF_STATUS for every buffer RW 0x0 RW 0x0 RW 0x0 completed on EP0 28 EP0_INT_2BUF Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 27 EP0_INT_NAK Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK 26 DIRECT_EN Direct bus drive enable RW 0x0 25 DIRECT_DP Direct control of DP RW 0x0 24 DIRECT_DM Direct control of DM RW 0x0 23:19 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 31 DATA_SEQ_ERRO Data Sequence Error.
RP2040 Datasheet Bits Name Description Type Reset 10 VBUS_OVER_CUR VBUS over current detected RO 0x0 R 9:8 SPEED Host: device speed. Disconnected = 00, LS = 01, FS = 10 RO 0x0 7:5 Reserved. - - - 4 SUSPENDED Bus in suspended state. Valid for device and host. Host RO 0x0 and device will go into suspend if neither Keep Alive / SOF frames are enabled. 3:2 LINE_STATE USB bus line state RO 0x0 1 Reserved.
RP2040 Datasheet Bits Name 20 Description Type Reset EP10_IN WC 0x0 19 EP9_OUT WC 0x0 18 EP9_IN WC 0x0 17 EP8_OUT WC 0x0 16 EP8_IN WC 0x0 15 EP7_OUT WC 0x0 14 EP7_IN WC 0x0 13 EP6_OUT WC 0x0 12 EP6_IN WC 0x0 11 EP5_OUT WC 0x0 10 EP5_IN WC 0x0 9 EP4_OUT WC 0x0 8 EP4_IN WC 0x0 7 EP3_OUT WC 0x0 6 EP3_IN WC 0x0 5 EP2_OUT WC 0x0 4 EP2_IN WC 0x0 3 EP1_OUT WC 0x0 2 EP1_IN WC 0x0 1 EP0_OUT WC 0x0 0 EP0_IN WC 0x0 USB: BUFF_CPU_
RP2040 Datasheet Bits Name 22 Description Type Reset EP11_IN RO 0x0 21 EP10_OUT RO 0x0 20 EP10_IN RO 0x0 19 EP9_OUT RO 0x0 18 EP9_IN RO 0x0 17 EP8_OUT RO 0x0 16 EP8_IN RO 0x0 15 EP7_OUT RO 0x0 14 EP7_IN RO 0x0 13 EP6_OUT RO 0x0 12 EP6_IN RO 0x0 11 EP5_OUT RO 0x0 10 EP5_IN RO 0x0 9 EP4_OUT RO 0x0 8 EP4_IN RO 0x0 7 EP3_OUT RO 0x0 6 EP3_IN RO 0x0 5 EP2_OUT RO 0x0 4 EP2_IN RO 0x0 3 EP1_OUT RO 0x0 2 EP1_IN RO 0x0 1 EP0_OUT
RP2040 Datasheet Bits Name 25 Description Type Reset EP12_OUT RW 0x0 24 EP12_IN RW 0x0 23 EP11_OUT RW 0x0 22 EP11_IN RW 0x0 21 EP10_OUT RW 0x0 20 EP10_IN RW 0x0 19 EP9_OUT RW 0x0 18 EP9_IN RW 0x0 17 EP8_OUT RW 0x0 16 EP8_IN RW 0x0 15 EP7_OUT RW 0x0 14 EP7_IN RW 0x0 13 EP6_OUT RW 0x0 12 EP6_IN RW 0x0 11 EP5_OUT RW 0x0 10 EP5_IN RW 0x0 9 EP4_OUT RW 0x0 8 EP4_IN RW 0x0 7 EP3_OUT RW 0x0 6 EP3_IN RW 0x0 5 EP2_OUT RW 0x0 4
RP2040 Datasheet Bits Name 27 Description Type Reset EP13_OUT WC 0x0 26 EP13_IN WC 0x0 25 EP12_OUT WC 0x0 24 EP12_IN WC 0x0 23 EP11_OUT WC 0x0 22 EP11_IN WC 0x0 21 EP10_OUT WC 0x0 20 EP10_IN WC 0x0 19 EP9_OUT WC 0x0 18 EP9_IN WC 0x0 17 EP8_OUT WC 0x0 16 EP8_IN WC 0x0 15 EP7_OUT WC 0x0 14 EP7_IN WC 0x0 13 EP6_OUT WC 0x0 12 EP6_IN WC 0x0 11 EP5_OUT WC 0x0 10 EP5_IN WC 0x0 9 EP4_OUT WC 0x0 8 EP4_IN WC 0x0 7 EP3_OUT WC 0x0
RP2040 Datasheet Table 420. EP_STALL_ARM Register Bits Name Description Type Reset 31:2 Reserved. - - - 1 EP0_OUT RW 0x0 0 EP0_IN RW 0x0 USB: NAK_POLL Register Offset: 0x6c Description Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. Table 421. NAK_POLL Register Bits Name Description Type Reset 31:26 Reserved. - - - 25:16 DELAY_FS NAK polling interval for a full speed device RW 0x010 15:10 Reserved.
RP2040 Datasheet Bits Name 14 Description Type Reset EP7_IN WC 0x0 13 EP6_OUT WC 0x0 12 EP6_IN WC 0x0 11 EP5_OUT WC 0x0 10 EP5_IN WC 0x0 9 EP4_OUT WC 0x0 8 EP4_IN WC 0x0 7 EP3_OUT WC 0x0 6 EP3_IN WC 0x0 5 EP2_OUT WC 0x0 4 EP2_IN WC 0x0 3 EP1_OUT WC 0x0 2 EP1_IN WC 0x0 1 EP0_OUT WC 0x0 0 EP0_IN WC 0x0 USB: USB_MUXING Register Offset: 0x74 Description Where to connect the USB controller. Should be to_phy by default. Table 423.
RP2040 Datasheet Bits Name 2 Description Type Reset VBUS_DETECT RW 0x0 1 VBUS_EN_OVERRIDE_EN RW 0x0 0 VBUS_EN RW 0x0 USB: USBPHY_DIRECT Register Offset: 0x7c Description This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. Table 425. USBPHY_DIRECT Register Bits Name Description Type Reset 31:23 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 7 Reserved. - - - 6 DM_PULLDN_EN DM pull down enable RW 0x0 5 DM_PULLUP_EN DM pull up enable RW 0x0 4 DM_PULLUP_HISE Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - RW 0x0 L Pull = Rpu1 + Rpu2 3 Reserved. - - - 2 DP_PULLDN_EN DP pull down enable RW 0x0 1 DP_PULLUP_EN DP pull up enable RW 0x0 0 DP_PULLUP_HISE Enable the second DP pull up resistor.
RP2040 Datasheet Table 427. USBPHY_TRIM Register Bits Name Description Type Reset 31:13 Reserved. - - - 12:8 DM_PULLDN_TRI Value to drive to USB PHY RW 0x1f M DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required 7:5 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 4 BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 clearing all bits in BUFF_STATUS. 3 TRANS_COMPLET Raised every time SIE_STATUS.TRANS_COMPLETE is set. 2 E Clear by writing to this bit. HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD 1 HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.
RP2040 Datasheet Bits Name Description Type Reset 5 ERROR_DATA_SE Source: SIE_STATUS.DATA_SEQ_ERROR RW 0x0 Raised when any bit in BUFF_STATUS is set. Clear by RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Q 4 BUFF_STATUS clearing all bits in BUFF_STATUS. 3 TRANS_COMPLET Raised every time SIE_STATUS.TRANS_COMPLETE is set. 2 E Clear by writing to this bit. HOST_SOF Host: raised every time the host sends a SOF (Start of Frame).
RP2040 Datasheet Bits Name Description Type Reset 6 ERROR_RX_TIME Source: SIE_STATUS.RX_TIMEOUT RW 0x0 Source: SIE_STATUS.DATA_SEQ_ERROR RW 0x0 Raised when any bit in BUFF_STATUS is set. Clear by RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 OUT 5 ERROR_DATA_SE Q 4 BUFF_STATUS clearing all bits in BUFF_STATUS. 3 TRANS_COMPLET Raised every time SIE_STATUS.TRANS_COMPLETE is set. 2 E Clear by writing to this bit. HOST_SOF Host: raised every time the host sends a SOF (Start of Frame).
RP2040 Datasheet Bits Name Description Type Reset 7 ERROR_RX_OVER Source: SIE_STATUS.RX_OVERFLOW RO 0x0 Source: SIE_STATUS.RX_TIMEOUT RO 0x0 Source: SIE_STATUS.DATA_SEQ_ERROR RO 0x0 Raised when any bit in BUFF_STATUS is set. Clear by RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 FLOW 6 ERROR_RX_TIME OUT 5 ERROR_DATA_SE Q 4 BUFF_STATUS clearing all bits in BUFF_STATUS. 3 2 TRANS_COMPLET Raised every time SIE_STATUS.TRANS_COMPLETE is set. E Clear by writing to this bit.
RP2040 Datasheet • Transmit data tx (referred to as UARTTXD in the following sections) • Received data rx (referred to as UARTRXD in the following sections) • Output flow control rts (referred to as nUARTRTS in the following sections) • Input flow control cts (referred to as nUARTCTS in the following sections) The modem mode and IrDA mode of the PL011 are not supported. The UARTCLK is driven from clk_peri, and PCLK is driven from the system clock clk_sys (see Section 2.15.1). 4.2.1.
RP2040 Datasheet Figure 59. UART block diagram. Test logic is not shown for clarity. 4.2.2.1. AMBA APB interface The AMBA APB interface generates read and write decodes for accesses to status/control registers, and the transmit and receive FIFOs. 4.2.2.2. Register block The register block stores data written, or to be read across the AMBA APB interface. 4.2.2.3. Baud rate generator The baud rate generator contains free-running counters that generate the internal clocks: Baud16 and IrLPBaud16 signals.
RP2040 Datasheet 4.2.2.6. Transmit logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream beginning with a start bit, data bits with the Least Significant Bit (LSB) first, followed by the parity bit, and then the stop bits according to the programmed configuration in control registers. 4.2.2.7.
RP2040 Datasheet 4.2.3.2. UART operation Control data is written to the UART Line Control Register, UARTLCR. This register is 30-bits wide internally, but is externally accessed through the APB interface by writes to the following registers: The UARTLCR_H register defines the: • transmission parameters • word length • buffer mode • number of transmitted stop bits • parity mode • break generation.
RP2040 Datasheet logic 0 pulses (half way through a bit period). The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled.
RP2040 Datasheet Figure 61. UART Data bits Start bit character frame. TXD 0 1 0 1 0 Stop bit 0 1 1 0 1 DMASREQ Bit period 3/16 Bit period 1 0 DMABREQ DMACLR 0 1 0 1 0 Start 0 Data bits 1 1 Stop 4.2.4. UART hardware flow control The hardware flow control feature is fully selectable, and enables you to control the serial data flow by using the nUARTRTS output and nUARTCTS input signals. Figure 62 shows how two devices can communicate with each other using hardware flow control.
RP2040 Datasheet The nUARTRTS signal is reasserted when data has been read out of the receive FIFO so that it is filled to less than the watermark level. If RTS flow control is disabled and the UART is still enabled, then data is received until the receive FIFO is full, or no more data is transmitted to it. 4.2.4.2. CTS flow control If CTS flow control is enabled, then the transmitter checks the nUARTCTS signal before transmitting the next byte.
RP2040 Datasheet NOTE For the remaining three characters the UART cannot assert the burst request. Each request signal remains asserted until the relevant DMACLR signal is asserted. After the request clear signal is deasserted, a request signal can become active again, depending on the conditions described previously. All request signals are deasserted if the UART is disabled or the relevant DMA enable bit, TXDMAE or RXDMAE, in the DMA Control Register, UARTDMACR, is cleared.
RP2040 Datasheet the FIFO trigger levels. The error interrupt, UARTEINTR, can be triggered when there is an error in the reception of data. A number of error conditions are possible. The modem status interrupt, UARTMSINTR, is a combined interrupt of all the individual modem status signals. The status of the individual interrupt sources can be read either from the Raw Interrupt Status Register, UARTRIS, or from the Masked Interrupt Status Register, UARTMIS. 4.2.6.1.
RP2040 Datasheet 4.2.6.5. UARTEINTR The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be caused by a number of different error conditions: • framing • parity • break • overrun. You can determine the cause of the interrupt by reading the Raw Interrupt Status Register, UARTRIS, or the Masked Interrupt Status Register, UARTMIS.
RP2040 Datasheet 57 uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS; 58 // Enable FIFOs 59 hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS); 60 // Always enable DREQ signals -- no harm in this if DMA is not listening 61 uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS; 62 63 return baud; 64 } 4.2.7.1. Baud Rate Calculation The uart baud rate is derived from dividing clk_peri.
RP2040 Datasheet 4.2.8. List of Registers The UART0 and UART1 registers start at base addresses of 0x40034000 and 0x40038000 respectively (defined as UART0_BASE and UART1_BASE in SDK). Table 435.
RP2040 Datasheet Bits Name Description Type Reset 10 BE Break error. This bit is set to 1 if a break condition was RO - RO - Framing error. When set to 1, it indicates that the received RO - detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO.
RP2040 Datasheet Bits Name Description Type Reset 1 PE Parity error. When set to 1, it indicates that the parity of WC 0x0 Framing error. When set to 1, it indicates that the received WC 0x0 the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
RP2040 Datasheet Bits Name Description Type Reset 3 BUSY UART busy. If this bit is set to 1, the UART is busy RO 0x0 RO - RO - RO - transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. 2 DCD Data carrier detect.
RP2040 Datasheet Table 441. UARTFBRD Register Bits Name Description Type Reset 31:6 Reserved. - - - 5:0 BAUD_DIVFRAC The fractional baud rate divisor. These bits are cleared to RW 0x00 0 on reset. UART: UARTLCR_H Register Offset: 0x02c Description Line Control Register, UARTLCR_H Table 442. UARTLCR_H Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 SPS Stick parity select.
RP2040 Datasheet Description Control Register, UARTCR Table 443. UARTCR Register Bits Name Description Type Reset 31:16 Reserved. - - - 15 CTSEN CTS hardware flow control enable. If this bit is set to 1, RW 0x0 RW 0x0 This bit is the complement of the UART Out2 (nUARTOut2) RW 0x0 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. 14 RTSEN RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled.
RP2040 Datasheet Bits Name Description Type Reset 7 LBE Loopback enable. If this bit is set to 1 and the SIREN bit is RW 0x0 set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal halfduplex SIR operation.
RP2040 Datasheet Bits Name Description Type Reset 5:3 RXIFLSEL Receive interrupt FIFO level select. The trigger points for RW 0x2 RW 0x2 the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. 2:0 TXIFLSEL Transmit interrupt FIFO level select.
RP2040 Datasheet Bits Name Description Type Reset 4 RXIM Receive interrupt mask. A read returns the current mask RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. 3 DSRMIM nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
RP2040 Datasheet Bits Name Description Type Reset 2 DCDRMIS nUARTDCD modem interrupt status. Returns the raw RO - RO - RO - interrupt state of the UARTDCDINTR interrupt. 1 CTSRMIS nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. 0 RIRMIS nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. UART: UARTMIS Register Offset: 0x040 Description Masked Interrupt Status Register, UARTMIS Table 447.
RP2040 Datasheet Bits Name Description Type Reset 31:11 Reserved. - - - 10 OEIC Overrun error interrupt clear. Clears the UARTOEINTR WC - WC - WC - WC - WC - interrupt. 9 BEIC Break error interrupt clear. Clears the UARTBEINTR interrupt. 8 PEIC Parity error interrupt clear. Clears the UARTPEINTR interrupt. 7 FEIC Framing error interrupt clear. Clears the UARTFEINTR interrupt. 6 RTIC Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
RP2040 Datasheet Table 450. UARTPERIPHID0 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 PARTNUMBER0 These bits read back as 0x11 RO 0x11 UART: UARTPERIPHID1 Register Offset: 0xfe4 Description UARTPeriphID1 Register Table 451. UARTPERIPHID1 Register Bits Name Description Type Reset 31:8 Reserved.
RP2040 Datasheet Table 454. UARTPCELLID0 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 UARTPCELLID0 These bits read back as 0x0D RO 0x0d UART: UARTPCELLID1 Register Offset: 0xff4 Description UARTPCellID1 Register Table 455. UARTPCELLID1 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 UARTPCELLID1 These bits read back as 0xF0 RO 0xf0 UART: UARTPCELLID2 Register Offset: 0xff8 Description UARTPCellID2 Register Table 456.
RP2040 Datasheet 4.3.1. Features Each I2C controller is based on a configuration of the Synopsys DW_apb_i2c (v2.01) IP. The following features are supported: • Master or Slave (Default to Master mode) • Standard mode, Fast mode or Fast mode plus • Default slave address 0x055 • Supports 10-bit addressing in Master mode • 16-element transmit buffer • 16-element receive buffer • Can be driven from DMA • Can generate interrupts 4.3.1.1.
RP2040 Datasheet • 10-bit addressing supported in master mode (7-bit by default) • 16 entry transmit buffer • 16 entry receive buffer • Allows restart conditions when a master (can be disabled for legacy device support) • Configurable timing to adjust TsuDAT/ThDAT • General calls responded to on reset • Interface to DMA • Single interrupt output • Configurable timing to adjust clock frequency • Spike suppression (default 7 clk_sys cycles) • Can NACK after data received by Slave • Hold transfer when TX FIFO
RP2040 Datasheet unpredictable states would occur. An example of high-speed mode devices are LCD displays, high-bit count ADCs, and high capacity EEPROMs. These devices typically need to transfer large amounts of data. Most maintenance and control applications, the common use for the I2C bus, typically operate at 100 kHz (in standard and fast modes). Any DW_apb_i2c device can be attached to an I2C-bus and every device can talk with any master, passing information back and forth.
RP2040 Datasheet • RX FIFO/TX FIFO — Holds the RX FIFO and TX FIFO register banks and controllers, along with their status levels. 4.3.4. I2C Terminology The following terms are used and are defined as follows: 4.3.4.1. I2C Bus Terms The following terms relate to how the role of the I2C device and how it interacts with other I2C devices on the bus. • Transmitter – the device that sends data to the bus.
RP2040 Datasheet either transmitting or receiving data to/from the master. The acknowledgement of data is sent by the device that is receiving data, which can be either a master or a slave. As mentioned previously, the I2C protocol also allows multiple masters to reside on the I2C bus and uses an arbitration procedure to determine bus ownership. Each slave has a unique address that is determined by the system designer.
RP2040 Datasheet 4.3.6. I2C Protocols The DW_apb_i2c has the protocols discussed in this section. 4.3.6.1. START and STOP Conditions When the bus is idle, both the SCL and SDA signals are pulled high through external pull-up resistors on the bus. When the master wants to start a transmission on the bus, the master issues a START condition. This is defined to be a high-tolow transition of the SDA signal while SCL is 1. When the master wants to terminate the transmission, the master issues a STOP condition.
RP2040 Datasheet Figure 68. 10-bit Address Format S ‘1’ ‘1’ ‘1’ ‘0’ A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK sent by slave sent by slave Reserved for 10-bit Address S = START Condition ACK = Acknowledge R/W = Read/Write Pulse This table defines the special purpose and reserved first byte addresses. Table 458. I2C/SMBus Definition of Bits in First Byte Slave Address R/W Bit 0000 000 0 Description General Call Address.
RP2040 Datasheet Figure 69. I2C MasterTransmitter Protocol For 7-bit Address S Slave Address R/W A DATA A DATA A/A P ‘0’ (read) For 10-bit Address S Slave Address First 7 bits ‘11110xxx’ R/W A Slave Address Second Byte A DATA A/A P ‘0’ (write) From Master to Slave A = Acknowledge (SDA low) S = START Condition From Slave to Master A = No Acknowledge (SDA high) P = STOP Condition 4.3.6.3.2.
RP2040 Datasheet Figure 71. I2C Start Byte Transfer dummy acknowledge SDA (HIGH) 1 SCL 2 7 8 9 Ack S Sr start byte 00000001 The START BYTE procedure is as follows: 1. Master generates a START condition. 2. Master transmits the START byte (0000 0001). 3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format used on the bus) 4. No slave sets the ACK signal to zero. 5. Master generates a RESTART (R) condition.
RP2040 Datasheet Figure 73.
RP2040 Datasheet Figure 78.
RP2040 Datasheet Figure 81. Multiple Master Arbitration MSB CLKA ‘1’ DATA1 loses arbitration matching data MSB DATA2 ‘0’ SDA mirrors DATA2 MSB SDA SCL SDA lines up with DATA1 START condition Control of the bus is determined by address or master code and data sent by competing masters, so there is no central master nor any order of priority on the bus.
RP2040 Datasheet 4.3.10. Operation Modes This section provides information on operation modes. NOTE It is important to note that the DW_apb_i2c should only be set to operate as an I2C Master, or I2C Slave, but not both simultaneously. This is achieved by ensuring that IC_CON.IC_SLAVE_DISABLE and IC_CON.IC_MASTER_MODE are never set to zero and one, respectively. 4.3.10.1. Slave Mode Operation This section discusses slave mode procedures. 4.3.10.1.1.
RP2040 Datasheet WARNING It is recommended that the DW_apb_i2c Slave be brought out of reset only when the I2C bus is IDLE. De-asserting the reset when a transfer is ongoing on the bus causes internal synchronization flip-flops used to synchronize SDA and SCL to toggle from a reset value of one to the actual value on the bus. This can result in SDA toggling from one to zero while SCL is one, thereby causing a false START condition to be detected by the DW_apb_i2c Slave.
RP2040 Datasheet 1. Software writes to the IC_DATA_CMD register with the data to be written (by writing a ‘0’ in bit 8). 2. Software must clear the RD_REQ and TX_ABRT interrupts (bits five and six, respectively) of the IC_RAW_INTR_STAT register before proceeding. If the RD_REQ and/or TX_ABRT interrupts have been masked, then clearing of the IC_RAW_INTR_STAT register will have already been performed when either the R_RD_REQ or R_TX_ABRT bit has been read as one. 3.
RP2040 Datasheet If the RD_REQ interrupt is masked, due to IC_INTR_STAT.M_RD_REQ set to zero, then it is recommended that a timing routine be used to activate periodic reads of the IC_RAW_INTR_STAT register. Reads of IC_RAW_INTR_STAT that return bit five (R_RD_REQ) set to one must be treated as the equivalent of the RD_REQ interrupt referred to in this section. This timing routine is similar to that described in Section 4.3.10.1.2.
RP2040 Datasheet NOTE Depending on the reset values chosen, steps two, three, four, and five may not be necessary because the reset values can be configured. The values stored are static and do not need to be reprogrammed if the DW_apb_i2c is disabled, with the exception of the transfer direction and data. 4.3.10.2.2. Master Transmit and Master Receive The DW_apb_i2c supports switching back and forth between reading and writing dynamically.
RP2040 Datasheet NOTE This step can be ignored if DW_apb_i2c is programmed to operate as an I2C slave only. 1. The variable POLL_COUNT is initialized to zero. 2. Set bit zero of the IC_ENABLE register to zero. 3. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant error code. 4. If IC_ENABLE_STATUS[0] is one, then sleep for t i2c_poll and proceed to the previous step.
RP2040 Datasheet NOTE There is a 2-stage synchronizer on the SCL input, but for the sake of simplicity this synchronization delay was not included in the timing diagram in Figure 83.
RP2040 Datasheet 1. Master sends a maximum of nine clock pulses to recover the bus LOW within those nine clocks. ◦ The number of clock pulses will vary with the number of bits that remain to be sent by the slave. As the maximum number of bits is nine, master sends up to nine clock pluses and allows the slave to recover it. ◦ The master attempts to assert a Logic 1 on the SDA line and check whether SDA is recovered. If the SDA is not recovered, it will continue to send a maximum of nine SCL clocks. 2.
RP2040 Datasheet Timing Parameter Symbol Standard Speed Fast Speed / Fast Speed Plus HIGH period of the SCL clock tHIGH IC_SS_SCL_HCNT IC_FS_SCL_HCNT Setup time for a repeated tSU;STA IC_SS_SCL_LCNT IC_FS_SCL_HCNT Hold time (repeated) START tHD;STA IC_SS_SCL_HCNT IC_FS_SCL_HCNT tSU;STO IC_SS_SCL_HCNT IC_FS_SCL_HCNT tBUF IC_SS_SCL_LCNT IC_FS_SCL_LCNT Spike length tSP IC_FS_SPKLEN IC_FS_SPKLEN Data hold time tHD;DAT IC_SDA_HOLD IC_SDA_HOLD Data setup time tSU;DAT IC_SDA_SETUP I
RP2040 Datasheet NOTE The total high time and low time of SCL generated by the DW_apb_i2c master is also influenced by the rise time and fall time of the SCL line, as shown in the illustration and equations in Figure 86. It should be noted that the SCL rise and fall time parameters vary, depending on external factors such as: • Characteristics of IO driver • Pull-up resistor value • Total capacitance on SCL line, and so on These characteristics are beyond the control of the DW_apb_i2c. Figure 86.
RP2040 Datasheet SCL_PERIOD_FS / (IC_HCNT_FS + IC_LCNT_FS) = IC_CLK_PERIOD IC_LCNT_FS × IC_CLK_PERIOD = MIN_SCL_LOWtime_FS Combined, the previous equations produce the following: IC_LCNT_FS × (SCL_PERIOD_FS / (IC_LCNT_FS + IC_HCNT_FS) ) = MIN_SCL_LOWtime_FS Solving for IC_LCNT_FS: IC_LCNT_FS × (2.5μs / (IC_LCNT_FS + 14) ) = 1.3μs The previous equation gives: IC_LCNT_FS = roundup(15.166) = 16 These calculations produce IC_LCNT_FS = 16 and IC_HCNT_FS = 14, giving an ic_clk value of: 2.
RP2040 Datasheet mode based on this clock. These values need updating according to the guidelines below.
RP2040 Datasheet For example, where the transfer count programmed into the DMA Controller is four. The DMA transfer consists of a series of four single transactions. If the DW_apb_i2c makes a transmit request to this channel, a single data item is written to the DW_apb_i2c TX FIFO. Similarly, if the DW_apb_i2c makes a receive request to this channel, a single data item is read from the DW_apb_i2c RX FIFO.
RP2040 Datasheet 4.3.
RP2040 Datasheet Offset Name Info 0xf8 IC_COMP_VERSION I2C Component Version Register 0xfc IC_COMP_TYPE I2C Component Type Register I2C: IC_CON Register Offset: 0x00 Description I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only.
RP2040 Datasheet Bits Name 6 IC_SLAVE_DISABL This bit controls whether I2C has its slave disabled, which RW E Description Type Reset 0x1 means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.
RP2040 Datasheet Bits Name Description Type Reset 2:1 SPEED These bits control at which speed the DW_apb_i2c RW 0x2 RW 0x1 operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
RP2040 Datasheet Bits Name Description Type Reset 11 SPECIAL This bit indicates whether software performs a Device-ID RW 0x0 RW 0x0 RW 0x055 or General Call or START BYTE command.
RP2040 Datasheet Table 465. IC_SAR Register Bits Name Description Type Reset 31:10 Reserved. - - - 9:0 IC_SAR The IC_SAR holds the slave address when the I2C is RW 0x055 operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
RP2040 Datasheet Bits Name 11 FIRST_DATA_BYT Indicates the first data byte received after the address E Description Type Reset RO 0x0 SC 0x0 phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2.
RP2040 Datasheet Bits Name Description Type 9 STOP This bit controls whether a STOP is issued after the byte is SC Reset 0x0 sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty.
RP2040 Datasheet Description Standard Speed I2C Clock SCL High Count Register Table 467. IC_SS_SCL_HCNT Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 IC_SS_SCL_HCNT This register must be set before any I2C bus transaction RW 0x0028 can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.
RP2040 Datasheet Table 468. IC_SS_SCL_LCNT Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 IC_SS_SCL_LCNT This register must be set before any I2C bus transaction RW 0x002f can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed.
RP2040 Datasheet Description Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register Table 470. IC_FS_SCL_LCNT Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 IC_FS_SCL_LCNT This register must be set before any I2C bus transaction RW 0x000d can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL.
RP2040 Datasheet Bits Name Description Type Reset 10 R_START_DET See IC_RAW_INTR_STAT for a detailed description of RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 R_START_DET bit. Reset value: 0x0 0x0 → R_START_DET interrupt is inactive 0x1 → R_START_DET interrupt is active 9 R_STOP_DET See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.
RP2040 Datasheet Bits Name Description Type Reset 2 R_RX_FULL See IC_RAW_INTR_STAT for a detailed description of RO 0x0 RO 0x0 RO 0x0 R_RX_FULL bit. Reset value: 0x0 0x0 → R_RX_FULL interrupt is inactive 0x1 → R_RX_FULL interrupt is active 1 R_RX_OVER See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 0x0 → R_RX_OVER interrupt is inactive 0x1 → R_RX_OVER interrupt is active 0 R_RX_UNDER See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.
RP2040 Datasheet Bits Name Description Type Reset 9 M_STOP_DET This bit masks the R_STOP_DET interrupt in RW 0x0 RW 0x0 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 IC_INTR_STAT register. Reset value: 0x0 0x0 → STOP_DET interrupt is masked 0x1 → STOP_DET interrupt is unmasked 8 M_ACTIVITY This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
RP2040 Datasheet Bits Name Description Type Reset 1 M_RX_OVER This bit masks the R_RX_OVER interrupt in IC_INTR_STAT RW 0x1 RW 0x1 register. Reset value: 0x1 0x0 → RX_OVER interrupt is masked 0x1 → RX_OVER interrupt is unmasked 0 M_RX_UNDER This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
RP2040 Datasheet Bits Name Description Type Reset 10 START_DET Indicates whether a START or RESTART condition has RO 0x0 RO 0x0 This bit captures DW_apb_i2c activity and stays set until it RO 0x0 occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
RP2040 Datasheet Bits Name Description Type Reset 6 TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is RO 0x0 RO 0x0 RO 0x0 unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
RP2040 Datasheet Bits Name Description Type Reset 3 TX_OVER Set during transmit if the transmit buffer is filled to RO 0x0 RO 0x0 RO 0x0 RO 0x0 IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
RP2040 Datasheet Offset: 0x38 Description I2C Receive FIFO Threshold Register Table 474. IC_RX_TL Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 RX_TL Receive FIFO Threshold Level. RW 0x00 Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer.
RP2040 Datasheet Table 476. IC_CLR_INTR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLR_INTR Read this register to clear the combined interrupt, all RO 0x0 individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
RP2040 Datasheet Table 479. IC_CLR_TX_OVER Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of RO 0x0 the IC_RAW_INTR_STAT register. Reset value: 0x0 I2C: IC_CLR_RD_REQ Register Offset: 0x50 Description Clear RD_REQ Interrupt Register Table 480. IC_CLR_RD_REQ Register Bits Name Description Type Reset 31:1 Reserved.
RP2040 Datasheet Table 482. IC_CLR_RX_DONE Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of RO 0x0 the IC_RAW_INTR_STAT register. Reset value: 0x0 I2C: IC_CLR_ACTIVITY Register Offset: 0x5c Description Clear ACTIVITY Interrupt Register Table 483. IC_CLR_ACTIVITY Register Bits Name Description Type Reset 31:1 Reserved.
RP2040 Datasheet Table 485. IC_CLR_START_DET Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLR_START_DET Read this register to clear the START_DET interrupt (bit RO 0x0 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0 I2C: IC_CLR_GEN_CALL Register Offset: 0x68 Description Clear GEN_CALL Interrupt Register Table 486. IC_CLR_GEN_CALL Register Bits Name Description Type Reset 31:1 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 1 ABORT When set, the controller initiates the transfer abort. - 0: RW 0x0 Controls whether the DW_apb_i2c is enabled. - 0: Disables RW 0x0 ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit.
RP2040 Datasheet When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 Table 488. IC_STATUS Register Bits Name Description Type Reset 31:7 Reserved. - - - 6 SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State RO 0x0 RO 0x0 RO 0x0 RO 0x0 Transmit FIFO Completely Empty.
RP2040 Datasheet Bits Name Description Type Reset 0 ACTIVITY I2C Activity Status. Reset value: 0x0 RO 0x0 0x0 → I2C is idle 0x1 → I2C is active I2C: IC_TXFLR Register Offset: 0x74 Description I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer.
RP2040 Datasheet The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. Table 491. IC_SDA_HOLD Register Bits Name Description Type Reset 31:24 Reserved.
RP2040 Datasheet Bits Name 15 ABRT_SLVRD_INT 1: When the processor side responds to a slave mode X Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
RP2040 Datasheet Bits Name 11 ABRT_MASTER_DI This field indicates that the User tries to initiate a Master S Description Type Reset RO 0x0 RO 0x0 RO 0x0 operation with the Master mode disabled.
RP2040 Datasheet Bits Name Type Reset 8 ABRT_HS_NORST This field indicates that the restart is disabled RO 0x0 ABRT_SBYTE_AC This field indicates that the Master has sent a START Byte RO 0x0 KDET and the START Byte was acknowledged (wrong behavior). RT Description (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
RP2040 Datasheet Bits Name 3 ABRT_TXDATA_N This field indicates the master-mode only bit. When the OACK Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
RP2040 Datasheet A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. Table 493. IC_SLV_DATA_NACK_ ONLY Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 NACK Generate NACK.
RP2040 Datasheet Table 495. IC_DMA_TDLR Register Bits Name Description Type Reset 31:4 Reserved. - - - 3:0 DMATDL Transmit Data Level. This bit field controls the level at RW 0x0 which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
RP2040 Datasheet Table 497. IC_SDA_SETUP Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 SDA_SETUP SDA Setup. It is recommended that if the required delay is RW 0x64 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.
RP2040 Datasheet Bits Name 2 SLV_RX_DATA_LO Slave Received Data Lost. This bit indicates if a SlaveST Description Type Reset RO 0x0 Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0.
RP2040 Datasheet Bits Name 1 SLV_DISABLED_W Slave Disabled While Busy (Transmit, Receive). This bit HILE_BUSY Description Type Reset RO 0x0 RO 0x0 indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0.
RP2040 Datasheet Description I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. Table 500. IC_FS_SPKLEN Register Bits Name Description Type Reset 31:8 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 6 HAS_DMA DMA handshaking signals are enabled RO 0x0 5 INTR_IO COMBINED Interrupt outputs RO 0x0 4 HC_COUNT_VALU Programmable count values for each mode. RO 0x0 MAX SPEED MODE = FAST MODE RO 0x0 APB data bus width is 32 bits RO 0x0 ES 3:2 MAX_SPEED_MO DE 1:0 APB_DATA_WIDT H I2C: IC_COMP_VERSION Register Offset: 0xf8 Description I2C Component Version Register Table 503.
RP2040 Datasheet • 8 deep Tx and Rx FIFOs • Interrupt generation to service FIFOs or indicate error conditions • Can be driven from DMA • Programmable clock rate • Programmable data size 4-16 bits Each controller can be connected to a number of GPIO pins as defined in the GPIO muxing Table 289 in Section 2.19.2.
RP2040 Datasheet Figure 87. PrimeCell SSPTXINTR SSP block diagram. For clarity, does not show the test logic.
RP2040 Datasheet When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion, and transmission to the attached slave or master respectively, through the SSPTXD pin. 4.4.2.5. Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep memory buffer. Received data from the serial interface are stored in the buffer until read out by the CPU across the AMBA APB interface.
RP2040 Datasheet 4.4.3.2. Configuring the SSP Following reset, the PrimeCell SSP logic is disabled and must be configured when in this state. It is necessary to program control registers SSPCR0 and SSPCR1 to configure the peripheral as a master or slave operating under one of the following protocols: • Motorola SPI • Texas Instruments SSI • National Semiconductor. The bit rate, derived from the external SSPCLK, requires the programming of the clock prescale register SSPCPSR. 4.4.3.3.
RP2040 Datasheet NOTE Since the maximum frequency for clk_peri on RP2040 (and hence the maximum frequency for SSPCLK) is 133 MHz, the maximum SCK output frequency is 133 / 2 = 66.5 MHz, and the maximum SCK input frequency is 133 / 12 = ~11.083 MHz. 4.4.3.5. Programming the SSPCR0 Control Register The SSPCR0 register is used to: • program the serial clock rate • select one of the three protocols • select the data word size, where applicable.
RP2040 Datasheet • Texas Instruments synchronous serial • Motorola SPI • National Semiconductor Microwire. For all formats, the serial clock, SSPCLKOUT, is held inactive while the PrimeCell SSP is idle, and transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSPCLKOUT is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period.
RP2040 Datasheet Figure 89. Texas Instruments synchronous serial frame format, SSPCLKOUT/SSPCLIN SSPFSSOUT/SSPFSSIN continuous transfer MSB SSPTXD/SSPRXD LSB 4 to 16 bits nSSPOE (=0) 4.4.3.9. Motorola SPI frame format The Motorola SPI interface is a four-wire interface where the SSPFSSOUT signal behaves as a slave select. The main feature of the Motorola SPI format is that you can program the inactive state and phase of the SSPCLKOUT signal using the SPO and SPH bits of the SSPSCR0 control register.
RP2040 Datasheet • the SSPFSSOUT signal is forced HIGH • the transmit data line SSPTXD is arbitrarily forced LOW • the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance • when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the SSPCLKOUT pad, active-LOW enable • when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the SSPCLKOUT pad, active-LOW enable.
RP2040 Datasheet Data is then captured on the falling edges and propagated on the rising edges of the SSPCLKOUT signal. In the case of a single word transfer, after all bits have been transferred, the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured. For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive data words and termination is the same as that of the single word transfer. 4.4.3.12.
RP2040 Datasheet However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write.
RP2040 Datasheet Figure 96. Microwire frame format, single transfer SSPCLKOUT/SSPCLIN SSPFSSOUT/SSPFSSIN MSB SSPTXD LSB 8- bit control 0 SSPRXD MSB LSB 4 to 16 bits output data nSSPOE Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the PrimeCell SSP to the off-chip slave device.
RP2040 Datasheet With respect to the SSPCLKIN rising edge on which the first bit of receive data is to be sampled by the PrimeCell SSP slave, SSPFSSIN must have a setup of at least two times the period of SSPCLK on which the PrimeCell SSP operates. With respect to the SSPCLKIN rising edge previous to this edge, SSPFSSIN must have a hold of at least one SSPCLK period. Figure 98.
RP2040 Datasheet Figure 100. PrimeCell SSP master coupled to an SPI slave PL022 configured as master SPI slave SSPTXD MOSI nSSPOE MISO SSPRXD SSPFSSOUT SSPFSSIN OV SSPCLKOUT SCK nSSPCTLOE SS SSPCLKIN OV Figure 101 shows a Motorola SPI configured as a master and interfaced to an instance of a PrimeCell SSP (PL022) configured as a slave. In this case, the slave Select Signal (SS) is permanently tied HIGH to configure it as a master.
RP2040 Datasheet SSPTXDMASREQ Single-character DMA transfer request, asserted by the SSP. This signal is asserted when there is at least one empty location in the transmit FIFO. SSPTXDMABREQ Burst DMA transfer request, asserted by the SSP. This signal is asserted when the transmit FIFO contains four characters or fewer. SSPTXDMACLR DMA request clear, asserted by the DMA controller, to clear the transmit request signals.
RP2040 Datasheet Offset Name Info 0x014 SSPIMSC Interrupt mask set or clear register, SSPIMSC on page 3-9 0x018 SSPRIS Raw interrupt status register, SSPRIS on page 3-10 0x01c SSPMIS Masked interrupt status register, SSPMIS on page 3-11 0x020 SSPICR Interrupt clear register, SSPICR on page 3-11 0x024 SSPDMACR DMA control register, SSPDMACR on page 3-12 0xfe0 SSPPERIPHID0 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0xfe4 SSPPERIPHID1 Peripheral identification regi
RP2040 Datasheet Description Control register 1, SSPCR1 on page 3-5 Table 508. SSPCR1 Register Bits Name Description Type Reset 31:4 Reserved. - - - 3 SOD Slave-mode output disable. This bit is relevant only in the RW 0x0 Master or slave mode select. This bit can be modified only RW 0x0 slave mode, MS=1.
RP2040 Datasheet Bits Name Description Type Reset 4 BSY PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x1 currently transmitting and/or receiving a frame or the transmit FIFO is not empty. 3 RFF Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. 2 RNE Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. 1 TNF Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.
RP2040 Datasheet Offset: 0x018 Description Raw interrupt status register, SSPRIS on page 3-10 Table 513. SSPRIS Register Bits Name Description Type Reset 31:4 Reserved.
RP2040 Datasheet Description DMA control register, SSPDMACR on page 3-12 Table 516. SSPDMACR Register Bits Name Description Type Reset 31:2 Reserved. - - - 1 TXDMAE Transmit DMA Enable. If this bit is set to 1, DMA for the RW 0x0 RW 0x0 transmit FIFO is enabled. 0 RXDMAE Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. SPI: SSPPERIPHID0 Register Offset: 0xfe0 Description Peripheral identification registers, SSPPeriphID0-3 on page 3-13 Table 517.
RP2040 Datasheet Table 520. SSPPERIPHID3 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 CONFIGURATION These bits read back as 0x00 RO 0x00 SPI: SSPPCELLID0 Register Offset: 0xff0 Description PrimeCell identification registers, SSPPCellID0-3 on page 3-16 Table 521. SSPPCELLID0 Register Bits Name Description Type Reset 31:8 Reserved.
RP2040 Datasheet 4.5. PWM 4.5.1. Overview Pulse width modulation (PWM) is a scheme where a digital signal provides a smoothly varying average voltage. This is achieved with positive pulses of some controlled width, at regular intervals. The fraction of time spent high is known as the duty cycle. This may be used to approximate an analog output, or control switchmode power electronics. The RP2040 PWM block has 8 identical slices.
RP2040 Datasheet • The 16 PWM channels (8 2-channel slices) appear on GPIO0 to GPIO15, in the order PWM0 A, PWM0 B, PWM1 A… • This repeats for GPIO16 to GPIO29. GPIO16 is PWM0 A, GPIO17 is PWM0 B, so on up to PWM6 B on GPIO29 • The same PWM output can be selected on two GPIO pins; the same signal will appear on each GPIO. • If a PWM B pin is used as an input, and is selected on multiple GPIO pins, then the PWM slice will see the logical OR of those two GPIO inputs 4.5.2.1.
RP2040 Datasheet Figure 105. The slice counts repeatedly Count from 0 to 3, which is 0 1 2 3 0 1 2 3 0 1 2 3 A configured as the TOP B value. The output waves therefore have a period of 4. Output A is high for 1 cycle in 4, The default behaviour of a PWM slice is to count upward until the value of the TOP register is reached, and then so the average output immediately wrap to 0.
RP2040 Datasheet 4.5.2.3. Double Buffering Figure 108 shows how a change in input value will produce a change in output duty cycle. This can be used to approximate some analog waveform such as a sine wave. Figure 108. The input value varies with each counter period: first Input (Count) Count TOP Counter compare level TOP / 3, then 2 × TOP / 3, and finally TOP + 1 Counter 2×TOP/3 for 100% duty cycle.
RP2040 Datasheet Figure 110. Each counter wrap causes the interrupt request Counter at top IRQ signal to assert. The processor enters its CC_A 0 interrupt handler, writes to its copy of CC_A latched 1 2 0 1 3 2 the CC register, and clears the interrupt. When the counter There is no limitation on what values can be written to CC or TOP, or when they are written.
RP2040 Datasheet Figure 112. PWM slice Event select event selection. The Phase Advance Phase Retard counter advances when its enable input 1 is high, and this enable is generated in two sequential stages. Input (pin B) EN First, any one of four Fractional Clock Divider (8.4) Count enable Rising edge event types (always on, pin B high, pin B rise, pin B fall) can Falling edge generate enable pulses for the fractional clock divider.
RP2040 Datasheet • The TOP register • Whether phase-correct mode is enabled (CSR_PH_CORRECT) • The DIV register The slice counts from 0 to TOP, and then either wraps, or begins counting backward, depending on the setting of CSR_PH_CORRECT. The rate of counting is slowed by the clock divider, with a maximum speed of one count per cycle, and a minimum speed of one count per cycles.
RP2040 Datasheet Figure 113. The clock enable signal, output Clock by the clock divider, controls the rate of counting. Phase 2 DIV_INT advance forces the Clock enable clock enable high on Count cycles where it is low, 0 1 2 3 4 5 4 5 6 2 3 4 causing the counter to jump forward by one forces the clock 2 DIV_INT count. Phase retard CSR_PH_ADV enable low when it Clock enable would be high, holding the counter back by Count 0 1 2 3 one count.
RP2040 Datasheet Offset Name Info 0x34 CH2_CC Counter compare values 0x38 CH2_TOP Counter wrap value 0x3c CH3_CSR Control and status register 0x40 CH3_DIV INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
RP2040 Datasheet Offset Name Info 0xa0 EN This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR.
RP2040 Datasheet Table 528. CH0_DIV, CH1_DIV, …, CH6_DIV, CH7_DIV Registers Bits Name Description Type Reset 31:12 Reserved. - - - 11:4 INT RW 0x01 3:0 FRAC RW 0x0 PWM: CH0_CTR, CH1_CTR, …, CH6_CTR, CH7_CTR Registers Offsets: 0x08, 0x1c, …, 0x80, 0x94 Table 529. CH0_CTR, CH1_CTR, …, CH6_CTR, CH7_CTR Registers Bits Description Type Reset 31:16 Reserved.
RP2040 Datasheet Bits Name 2 Description Type Reset CH2 RW 0x0 1 CH1 RW 0x0 0 CH0 RW 0x0 PWM: INTR Register Offset: 0xa4 Description Raw Interrupts Table 533. INTR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 CH7 WC 0x0 6 CH6 WC 0x0 5 CH5 WC 0x0 4 CH4 WC 0x0 3 CH3 WC 0x0 2 CH2 WC 0x0 1 CH1 WC 0x0 0 CH0 WC 0x0 PWM: INTE Register Offset: 0xa8 Description Interrupt Enable Table 534.
RP2040 Datasheet Description Interrupt Force Table 535. INTF Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 CH7 RW 0x0 6 CH6 RW 0x0 5 CH5 RW 0x0 4 CH4 RW 0x0 3 CH3 RW 0x0 2 CH2 RW 0x0 1 CH1 RW 0x0 0 CH0 RW 0x0 PWM: INTS Register Offset: 0xb0 Description Interrupt status after masking & forcing Table 536. INTS Register Bits Name Description Type Reset 31:8 Reserved.
RP2040 Datasheet the reference clock (Figure 28), which itself is usually connected directly to the crystal oscillator (Section 2.16). The 64-bit counter effectively can not overflow (thousands of years at 1 MHz), so the system timer is completely monotonic in practice. 4.6.1.1. Other Timer Resources on RP2040 The system timer is intended to provide a global timebase for software. RP2040 has a number of other programmable counter resources which can provide regular interrupts, or trigger DMA transfers.
RP2040 Datasheet Once the alarm has fired, the ARMED bit will be set to 0. To clear the latched interrupt, write a 1 to the appropriate bit in INTR. 4.6.4. Programmer’s Model NOTE The Watchdog tick (see Section 4.7.2) must be running for the timer to start counting. The SDK starts this tick as part of the platform initialisation code. 4.6.4.1. Reading the time NOTE Time here refers to the number of microseconds since the timer was started, it is not a clock. For that - see Section 4.8.
RP2040 Datasheet 51 } while (true); 52 return ((uint64_t) hi << 32u) | lo; 53 } 4.6.4.2. Set an alarm The standalone timer example, timer_lowlevel, demonstrates how to set an alarm at a hardware level, without the additional abstraction over the timer that the SDK provides. To use these abstractions see Section 4.6.4.4. Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/timer/timer_lowlevel/timer_lowlevel.
RP2040 Datasheet 4.6.4.3. Busy wait If you don’t want to use an alarm to wait for a period of time, instead use a while loop. The SDK provides various busy_wait_ functions to do this: SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_timer/timer.
RP2040 Datasheet 12 13 int64_t alarm_callback(alarm_id_t id, void *user_data) { 14 printf("Timer %d fired!\n", (int) id); 15 timer_fired = true; 16 // Can return a value here in us to fire in the future 17 return 0; 18 } 19 20 bool repeating_timer_callback(struct repeating_timer *t) { 21 printf("Repeat at %lld\n", time_us_64()); 22 return true; 23 } 24 25 int main() { 26 stdio_init_all(); 27 printf("Hello Timer!\n"); 28 29 // Call alarm_callback in 2 seconds 30 add_alarm_in_ms(2000, alar
RP2040 Datasheet Offset Name Info 0x08 TIMEHR Read from bits 63:32 of time always read timelr before timehr 0x0c TIMELR Read from bits 31:0 of time 0x10 ALARM0 Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x14 ALARM1 Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
RP2040 Datasheet Table 539. TIMELW Register Bits Description Type Reset 31:0 Write to bits 31:0 of time WF 0x00000000 writes do not get copied to time until timehw is written TIMER: TIMEHR Register Offset: 0x08 Table 540. TIMEHR Register Bits Description Type Reset 31:0 Read from bits 63:32 of time RO 0x00000000 always read timelr before timehr TIMER: TIMELR Register Offset: 0x0c Table 541.
RP2040 Datasheet Table 545. ALARM3 Register Bits Description Type Reset 31:0 Arm alarm 3, and configure the time it will fire. RW 0x00000000 Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. TIMER: ARMED Register Offset: 0x20 Table 546. ARMED Register Bits Description Type Reset 31:4 Reserved. - - 3:0 Indicates the armed/disarmed status of each alarm.
RP2040 Datasheet Table 550. PAUSE Register Bits Description Type Reset 31:1 Reserved. - - 0 Set high to pause the timer RW 0x0 TIMER: INTR Register Offset: 0x34 Description Raw Interrupts Table 551. INTR Register Bits Name Description Type Reset 31:4 Reserved. - - - 3 ALARM_3 WC 0x0 2 ALARM_2 WC 0x0 1 ALARM_1 WC 0x0 0 ALARM_0 WC 0x0 TIMER: INTE Register Offset: 0x38 Description Interrupt Enable Table 552.
RP2040 Datasheet Description Interrupt status after masking & forcing Table 554. INTS Register Bits Name Description Type Reset 31:4 Reserved. - - - 3 ALARM_3 RO 0x0 2 ALARM_2 RO 0x0 1 ALARM_1 RO 0x0 0 ALARM_0 RO 0x0 4.7. Watchdog 4.7.1. Overview The watchdog is a countdown timer that can restart parts of the chip if it reaches zero. This can be used to restart the processor if software gets stuck in an infinite loop.
RP2040 Datasheet WARNING Due to a logic error, the watchdog counter is decremented twice per tick. Which means the programmer needs to program double the intended count down value. The SDK examples take this issue into account. See RP2040-E1 for more information. 4.7.4. Scratch Registers The watchdog contains eight 32-bit scratch registers that can be used to store information between soft resets of the chip.
RP2040 Datasheet 4.7.5.2. Updating the watchdog counter SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_watchdog/watchdog.c Lines 23 - 27 23 static uint32_t load_value; 24 25 void watchdog_update(void) { 26 watchdog_hw->load = load_value; 27 } 4.7.5.3. Usage The Pico Examples repository provides a hello_watchdog example that uses the hardware_watchdog to demonstrate use of the watchdog. Pico Examples: https://github.
RP2040 Datasheet Offset Name Info 0x14 SCRATCH2 Scratch register 0x18 SCRATCH3 Scratch register 0x1c SCRATCH4 Scratch register 0x20 SCRATCH5 Scratch register 0x24 SCRATCH6 Scratch register 0x28 SCRATCH7 Scratch register 0x2c TICK Controls the tick generator WATCHDOG: CTRL Register Offset: 0x00 Description Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. Table 556.
RP2040 Datasheet Table 558. REASON Register Bits Name Description Type Reset 31:2 Reserved. - - - 1 FORCE RO 0x0 0 TIMER RO 0x0 WATCHDOG: SCRATCH0, SCRATCH1, …, SCRATCH6, SCRATCH7 Registers Offsets: 0x0c, 0x10, …, 0x24, 0x28 Table 559. SCRATCH0, SCRATCH1, …, SCRATCH6, SCRATCH7 Registers Bits Description Type Reset 31:0 Scratch register. Information persists through soft reset of the chip.
RP2040 Datasheet The RTC does not check that the programmed values are in range. Illegal values may cause unexpected behaviour. 4.8.1.1. Day of the week Day of the week is encoded as Sun 0, Mon 1, …, Sat 6 (i.e. ISO8601 mod 7). There is no built-in calendar function. The RTC will not compute the correct day of the week; it will only increment the existing value. 4.8.2.
RP2040 Datasheet NOTE All RTC register reads and writes are done from the processor clock domain clk_sys. All data are synchronised back and forth between the domains. Writing to the RTC will take 2 clk_rtc clock periods to arrive, additional to the clk_sys domain. This should be taken into account especially when the reference is slow (e.g. 1 Hz). 4.8.5. Programmer’s Model There are three setup tasks: • Set the 1 sec reference • Set the clock • Set an alarm 4.8.5.1.
RP2040 Datasheet 65 } 66 67 // Write to setup registers 68 rtc_hw->setup_0 = (((uint)t->year) 69 << RTC_SETUP_0_YEAR_LSB ) | (((uint)t->month) << RTC_SETUP_0_MONTH_LSB) | 70 (((uint)t->day) << RTC_SETUP_0_DAY_LSB); 71 rtc_hw->setup_1 = (((uint)t->dotw) << RTC_SETUP_1_DOTW_LSB) | 72 (((uint)t->hour) << RTC_SETUP_1_HOUR_LSB) | 73 (((uint)t->min) << RTC_SETUP_1_MIN_LSB) 74 (((uint)t->sec) << RTC_SETUP_1_SEC_LSB); | 75 76 // Load setup values into rtc clock domain 77 rtc_hw->ctrl =
RP2040 Datasheet 4.8.5.4. Configuring an Alarm SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_rtc/rtc.
RP2040 Datasheet • Sleep mode, where the processors are asleep and the unused clocks in the chip are stopped (see Section 2.15.3.5) • Dormant mode, where all clocks in the chip are stopped The RTC can wake the chip up from both of these modes. In sleep mode, RP2040 can be configured such that only clk_rtc (a slow RTC reference clock) is running, as well as a small amount of logic that allows the processor to wake back up. The processor is woken from sleep mode when the RTC alarm interrupt fires.
RP2040 Datasheet Table 563. CLKDIV_M1 Register Bits Description Type Reset 31:16 Reserved. - - 15:0 Divider minus 1 for the 1 second counter. Safe to change the value when RTC RW 0x0000 is not enabled. RTC: SETUP_0 Register Offset: 0x04 Description RTC setup register 0 Table 564. SETUP_0 Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:12 YEAR Year RW 0x000 11:8 MONTH Month (1..12) RW 0x0 7:5 Reserved. - - - 4:0 DAY Day of the month (1..
RP2040 Datasheet Bits Name Description Type Reset 4 LOAD Load RTC SC 0x0 3:2 Reserved. - - - 1 RTC_ACTIVE RTC enabled (running) RO - 0 RTC_ENABLE Enable RTC RW 0x0 RTC: IRQ_SETUP_0 Register Offset: 0x10 Description Interrupt setup register 0 Table 567. IRQ_SETUP_0 Register Bits Name Description Type Reset 31:30 Reserved. - - - 29 MATCH_ACTIVE RO - 28 MATCH_ENA RW 0x0 Global match enable. Don’t change any other value while this one is enabled 27 Reserved.
RP2040 Datasheet Bits Name Description Type Reset 13:8 MIN Minutes RW 0x00 7:6 Reserved. - - - 5:0 SEC Seconds RW 0x00 RTC: RTC_1 Register Offset: 0x18 Description RTC register 1. Table 569. RTC_1 Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:12 YEAR Year RO - 11:8 MONTH Month (1..12) RO - 7:5 Reserved. - - - 4:0 DAY Day of the month (1..
RP2040 Datasheet Table 571. INTR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 RTC RO 0x0 RTC: INTE Register Offset: 0x24 Description Interrupt Enable Table 572. INTE Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 RTC RW 0x0 RTC: INTF Register Offset: 0x28 Description Interrupt Force Table 573. INTF Register Bits Name Description Type Reset 31:1 Reserved.
RP2040 Datasheet • Interrupt generation • DMA interface (see Section 4.9.2.5) Figure 114. ADC Connection Diagram NOTE When using an ADC input shared with a GPIO pin, the pin’s digital functions must be disabled by setting IE low and OD high in the pin’s pad control register. See Section 2.19.6.3, “Pad Control - User Bank” for details. The maximum ADC input voltage is determined by the digital IO supply voltage (IOVDD), not the ADC supply voltage (ADC_AVDD). For example, if IOVDD is powered at 1.
RP2040 Datasheet 4.9.2. SAR ADC The SAR ADC (Successive Approximation Register Analogue to Digital Converter) is a combination of digital controller, and analogue circuit as show in Figure 115. Figure 115. SAR ADC Block diagram The ADC requires a 48MHz clock (clk_adc), which could come from the USB PLL. Capturing a sample takes 96 clock cycles (96 x 1 / 48MHz) = 2 μs per sample (500kS/s). The clock must be set up correctly before enabling the ADC.
RP2040 Datasheet the ADC will start a new conversion once per between and cycles on average, by changing the sample interval . 4.9.2.3. Sampling Multiple Inputs CS.RROBIN allows the ADC to sample multiple inputs, in an interleaved fashion, while performing free-running sampling. Each bit in RROBIN corresponds to one of the five possible values of CS.AINSEL. When the ADC completes a conversion, CS.AINSEL will automatically cycle to the next input whose corresponding bit is set in RROBIN.
RP2040 Datasheet CAUTION Conversion errors produce undefined results, and the corresponding sample should be discarded. They indicate that the comparison of one or more bits failed to complete in the time allowed. Normally this is caused by comparator metastability, i.e. the closer to the comparator threshold the input signal is, the longer it will take to make a decision. The high gain of the comparator reduces the probability that no decision is made. 4.9.2.5. DMA The RP2040 DMA (Section 2.
RP2040 Datasheet Parameter Value FFT bins 4,096 FFT averaging none Input level min 1 Input level max 4,094 Input frequency 997 Hz It should be noted that THD is normally calculated using the first 5 or 6 harmonics. However as INL/DNL errors (see Section 4.9.4) create more than this, the first 30 peaks are used. This makes the THD value slightly worse, but more representative of reality. Table 576. Results for Min Typical Max THD1 -55.6dB 55dB -54.4dB SNR 60.9dB 61.5dB 62.
RP2040 Datasheet Nominally an ADC moves from one digital value to the next digital value, colloquially expressed as “no missing codes”. However, if the ADC skips a value bin this would cause a spike in the Differential Non-Linearity (DNL) error. These types of error often only occur at specific codes due to the design of the ADC. The RP2040 ADC has a DNL which is mostly flat, and below 1 LSB. However at four values — 512, 1,536, 2,560, and 3,584 — the ADC’s DNL error peaks, see Figure 117 Figure 117.
RP2040 Datasheet NOTE The INL errors, see Section 4.9.4, aren’t in the usable temperature range of the ADC. 4.9.6. List of Registers The ADC registers start at a base address of 0x4004c000 (defined as ADC_BASE in SDK). Table 577. List of ADC registers Offset Name Info 0x00 CS ADC Control and Status 0x04 RESULT Result of most recent ADC conversion 0x08 FCS FIFO control and status 0x0c FIFO Conversion result FIFO 0x10 DIV Clock divider.
RP2040 Datasheet Bits Name Description Type Reset 9 ERR The most recent ADC conversion encountered an error; RO 0x0 RO 0x0 result is undefined or noisy. 8 READY 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress. 7:4 Reserved. - - - 3 START_MANY Continuously perform conversions whilst this bit is 1. A RW 0x0 SC 0x0 new conversion will start immediately after the previous finishes.
RP2040 Datasheet Bits Name Description Type Reset 1 SHIFT If 1: FIFO results are right-shifted to be one byte in size. RW 0x0 If 1: write result to the FIFO after each conversion. RW 0x0 Enables DMA to byte buffers. 0 EN ADC: FIFO Register Offset: 0x0c Description Conversion result FIFO Table 581. FIFO Register Bits Name Description Type Reset 31:16 Reserved. - - - 15 ERR 1 if this particular sample experienced a conversion error.
RP2040 Datasheet Description Interrupt Enable Table 584. INTE Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 FIFO Triggered when the sample FIFO reaches a certain level. RW 0x0 This level can be programmed via the FCS_THRESH field. ADC: INTF Register Offset: 0x1c Description Interrupt Force Table 585. INTF Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 FIFO Triggered when the sample FIFO reaches a certain level.
RP2040 Datasheet Motorola Serial Peripheral Interface (SPI) A four-wire, full-duplex serial protocol from Motorola. There are four possible combinations for the serial clock phase and polarity. The clock phase (SCPH) determines whether the serial transfer begins with the falling edge of the slave select signal or the first edge of the serial clock. The slave select line is held high when the DW_apb_ssi is idle or disabled. Texas Instruments Serial Protocol (SSP) A four-wire, full-duplex serial protocol.
RP2040 Datasheet • National Semiconductor Microwire On RP2040, the DW_apb_ssi is a component of the flash execute-in-place subsystem (see Section 2.6.3), and provides communication with an external SPI, dual-SPI or quad-SPI flash device. 4.10.2.1.
RP2040 Datasheet 4.10.3.1. Example of Target Slave Selection Using Software The following example is pseudo code that illustrates how to use software to select the target slave.
RP2040 Datasheet Figure 119. Maximum capture sclk_out/ssi_clk Ratio. drive1 capture1 drive2 capture2 drive3 capture3 ssi_clk sclk_out txd/rxd MSB The sclk_out line toggles only when an active transfer is in progress. At all other times it is held in an inactive state, as defined by the serial protocol under which it operates.
RP2040 Datasheet Table 587 provides description for different Transmit FIFO Threshold values. Table 587.
RP2040 Datasheet Transmit FIFO Overflow Interrupt (ssi_txo_intr) Set when an APB access attempts to write into the transmit FIFO after it has been completely filled. When set, data written from the APB is discarded. This interrupt remains set until you read the transmit FIFO overflow interrupt clear register (TXOICR). Receive FIFO Full Interrupt (ssi_rxf_intr) Set when the receive FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow.
RP2040 Datasheet entered. 4.10.8.3. Receive Only When TMOD = 10b, the transmit data are invalid. When configured as a slave, the transmit FIFO is never popped in Receive Only mode. The txd output remains at a constant logic level during the transmission. The data transfer occurs as normal according to the selected frame format (serial protocol). The receive data from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame.
RP2040 Datasheet Figure 120. DW_apb_ssi Configured as Master Device DW_apb_ssi Master 1 Slave Peripheral 1 DI txd DO ssi_oe_n SCLK rxd SS sclk_out ss_n[0] Slave Peripheral n ss_n[1] ss_in_n DI DO Glue Logic SCLK SS Should be driven to inactive level (protocol-dependent) in single master systems; may not need glue logic The serial bit-rate clock, generated and controlled by the DW_apb_ssi, is driven out on the sclk_out line.
RP2040 Datasheet that the setup times on the rxd signal are within range; this results in reducing the frequency of the serial interface. When the RXD Sample Delay logic is included, the user can dynamically program a delay value in order to move the sampling time of the rxd signal equal to a number of ssi_clk cycles from the default. The sample delay logic has a resolution of one ssi_clk cycle.
RP2040 Datasheet NOTE EEPROM read mode is not supported when the DW_apb_ssi is configured to be in the SSP mode. The receive FIFO threshold level (RXFTLR) can be used to give early indication that the receive FIFO is nearly full. When a DMA is used for APB accesses, the receive data level (DMARDLR) can be used to early request (dma_rx_req) the DMA Controller, indicating that the receive FIFO is nearly full.
RP2040 Datasheet Figure 122. Software Flow DW_apb_ssi Master SPI/SSP Transfer Flow IDLE Disable DW_apb_ssi DW_apb_ssi IDLE Configure Master by writing CTRLR0. CTRLR1, BAUDR, TXFTLR, RXFTLR, IMR, SER, SPI_CTRLR0 (if Dual /Quad SPI) Pop data from Tx FIFO into shifter Enable DW_apb_ssi Transfer Bit You may fill FIFO here: Transfer begins when first data word is present in the transmit FIFO and slave is enabled.
RP2040 Datasheet You can write the SER register to enable the target slave for selection. If a slave is enabled here, the transfer begins as soon as one valid data entry is present in the transmit FIFO. If no slaves are enabled prior to writing to the DR register, the transfer does not begin until a slave is enabled. 3. Enable the DW_apb_ssi by writing 1 to the SSIENR register. 4. If the DW_apb_ssi master transmits data, write the control and data words into the transmit FIFO (write DR).
RP2040 Datasheet clock is high or low. To transmit data, both SPI peripherals must have identical serial clock phase (SCPH) and clock polarity (SCPOL) values. The data frame can be 4 to 16/32 bits (depending upon SSI_MAX_XFER_SIZE) in length. When the configuration parameter SCPH = 0, data transmission begins on the falling edge of the slave select signal.
RP2040 Datasheet Figure 126 shows the timing diagram for the SPI format when the configuration parameter SCPH = 1. Figure 126. SPI Serial Format (SCPH = 1) sclk_out/in 0 sclk_out/in 1 txd MSB rxd MSB LSB 4 -32 bits LSB ss_0_n/ss_in_n ssi_oe_n Continuous data frames are transferred in the same way as single frames, with the MSB of the next frame following directly after the LSB of the current frame. The slave select signal is held active for the duration of the transfer.
RP2040 Datasheet Figure 129.
RP2040 Datasheet Figure 131. FIFO rxd Status for EEPROM Read Transfer Mode Write DR Tx FIFO Empty Tx FIFO Buffer Location n NULL Location 3 NULL Location n NULL SHIFT LOGIC Location 2 Address[7:0] Location 7 Rx_Data(7) Location 1 Address[15:8] Location 6 Rx_Data(6) Location 0 Opcode Location 1 Rx_Data(1) Location 0 Rx_Data(0) Rx FIFO Empty FIFO Status Prior to Transfer Rx FIFO Buffer txd Read DR FIFO Status on Completion of Transfer 4.10.10.2.
RP2040 Datasheet The direction of the data word is controlled by the MDD bit field (bit 1) in the Microwire Control Register (MWCR). When MDD=0, this indicates that the DW_apb_ssi serial master receives data from the external serial slave. One clock cycle after the LSB of the control word is transmitted, the slave peripheral responds with a dummy 0 bit, followed by the data frame, which can be four to 32 bits in length.
RP2040 Datasheet Figure 137.
RP2040 Datasheet Figure 140. Single Microwire Transfer sclk_out (transmitting data Control word frame) MSB txd Data word 0 LSB LSB MSB rxd ss_0_n ssi_oe_n NOTE The DW_apb_ssi does not support continuous sequential Microwire writes, where MDD = 1 and MWMOD = 1. Figure 141 shows how the data and control frames are structured in the transmit FIFO prior to the transfer, also shown is the value programmed into the MWCR register. Figure 141.
RP2040 Datasheet Figure 143.
RP2040 Datasheet Figure 146. Microwire Control Word sclk_out Control Word 0 txd MSB LSB rxd Start Bit Busy Ready ss_0_n ssi_oe_n 4.10.10.4. Enhanced SPI Modes DW_apb_ssi supports the dual and quad modes of SPI in RP2040; octal mode is not supported. txd, rxd and ssi_oe_n signals are four bits wide. Data is shifted out/in on more than one line, increasing the overall throughput.
RP2040 Datasheet Figure 147. Typical Write Operation Dual/Quad SPI Mode sclk_out txd[N:0] INSTRUCTION ADDRESS DATA ssi_oe_n[N:0] ss_oe_n To initiate a Dual/Quad write operation, CTRLR0.SPI_FRF must be set to 01/10/11, respectively. This will set the transfer type, and for each write command, data will be transferred in the format specified in CTLR0.SPI_FRF field. Case A: Instruction and address both transmitted in standard SPI format For this, SPI_CTRLR0.TRANS_TYPE field must be set to 00b.
RP2040 Datasheet 4.10.10.4.2. Read Operation in Enhanced SPI Modes A Dual, or Quad, SPI read operation can be divided into four phases: • Instruction phase • Address phase • Wait cycles • Data phase Wait Cycles can be programmed using SPI_CTRLR0.WAIT_CYCLES field. The value programmed into SPI_CTRLR0.WAIT_CYCLES is mapped directly to sclk_out times. For example, WAIT_CYCLES=0 indicates no Wait, WAIT_CYCLES=1, indicates one wait cycle and so on.
RP2040 Datasheet Case C: Instruction and Address both transmitted in Dual SPI format For this, SPI_CTRLR0.TRANS_TYPE field must be set to 10b. Figure 155 shows the timing diagram in which both instruction and address are transmitted in dual SPI format. The value of N will be: 7 if CTRLR0.SPI_FRF is set to 11b, 3 if CTRLR0.SPI_FRF is set to 10b, and 1 if CTRLR0.SPI_FRF is set to 01b. Figure 155.
RP2040 Datasheet 4.10.10.4.3. Advanced I/O Mapping for Enhanced SPI Modes The Input/Output mapping for enhanced SPI modes (dual, and quad) is hardcoded inside the DW_apb_ssi. The rxd[1] signal will be used to sample incoming data in standard SPI mode of operation. For other protocols (such as SSP and Microwire), the I/O mapping remains the same.
RP2040 Datasheet Figure 158. DDR Transfer with SCPH=0 sclk_out and SCPOL=0 ss_oe_n A3 INST txd[N:0] A2 A1 A0 D3 D2 D1 D0 rxd[N:0] ss_oe_n[N:0] INST = Instruction Phase A3, A2, A1, A0 = Address Bytes D3, D2, D1, D0 = Data Bytes Figure 159 describes a DDR write transfer where instruction, address and data all are transferred in DDR format. Figure 159.
RP2040 Datasheet Figure 161. Transmit Data With DDR_DRIVE_EDGE = 1 ssi_clk sclk_out ss_0_n txd[N:0] INST A3 A2 A1 A0 D3 D2 D1 D0 rxd[N:0] ssi_oe_n[N:0] INST = Instruction Phase A3, A2, A1, A0 = Address Bytes D3, D2, D1, D0 = Data Bytes Figure 162. Transmit Data With DDR_DRIVE_EDGE = 2 ssi_clk sclk_out ss_0_n txd[N:0] INST A3 A2 A1 A0 D3 D2 D1 D0 rxd[N:0] ssi_oe_n[N:0] INST = Instruction Phase A3, A2, A1, A0 = Address Bytes D3, D2, D1, D0 = Data Bytes 4.10.10.6.
RP2040 Datasheet Figure 163. Typical Read Operation in XIP Mode 4.10.11. DMA Controller Interface The DW_apb_ssi has built-in DMA capability; it has a handshaking interface to a DMA Controller to request and control transfers. The APB bus is used to perform the data transfer to or from the DMA. NOTE When the DW_apb_ssi interfaces to the DMA controller, the DMA controller is always a flow controller; that is, it controls the block size. This must be programmed by software in the DMA controller.
RP2040 Datasheet 0000_0010 dma_tx_req is asserted when two or less data entries are present in the transmit FIFO … … 0000_1101 dma_tx_req is asserted when 13 or less data entries are present in the transmit FIFO 0000_1110 dma_tx_req is asserted when 14 or less data entries are present in the transmit FIFO 0000_1111 dma_tx_req is asserted when 15 or less data entries are present in the transmit FIFO Table 591 provides description for different DMA Receive Data Level values. Table 591.
RP2040 Datasheet Figure 164. 12 Data Items Breakdown of DMA Transfer into Burst Transactions. Block DMA size, DMA.CTLx.BLOCKS Multi-block Transfer _TS = 12. Number of Level data items per source burst transaction, 12 Data Items DMA.CTLx.SRC_MS IZE = 4. SSI receive DMA FIFO watermark level, SSI.DMARDLR + 1 = Block DMA.CTLx.
RP2040 Datasheet read operation from DR moves data from the receive FIFO buffer onto prdata. The DW_apb_ssi DR can be written/read in one APB access. NOTE The DR register in the DW_apb_ssi occupies sixty-four 32-bit locations of the memory map to facilitate AHB burst transfers. There are no burst transactions on the APB bus itself, but DW_apb_ssi supports the AHB bursts that happen on the AHB side of the AHB/APB bridge.
RP2040 Datasheet Offset Name Info 0x60 DR0 Data Register 0 (of 36) 0xf0 RX_SAMPLE_DLY RX sample delay 0xf4 SPI_CTRLR0 SPI control 0xf8 TXD_DRIVE_EDGE TX drive edge SSI: CTRLR0 Register Offset: 0x00 Description Control register 0 Table 593. CTRLR0 Register Bits Name Description Type Reset 31:25 Reserved. - - - 24 SSTE Slave select toggle enable RW 0x0 23 Reserved.
RP2040 Datasheet Description Master Control register 1 Table 594. CTRLR1 Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 NDF Number of data frames RW 0x0000 SSI: SSIENR Register Offset: 0x08 Description SSI Enable Table 595. SSIENR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 SSI_EN SSI enable RW 0x0 SSI: MWCR Register Offset: 0x0c Description Microwire Control Table 596.
RP2040 Datasheet Table 598. BAUDR Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 SCKDV SSI clock divider RW 0x0000 SSI: TXFTLR Register Offset: 0x18 Description TX FIFO threshold level Table 599. TXFTLR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 TFT Transmit FIFO threshold RW 0x00 SSI: RXFTLR Register Offset: 0x1c Description RX FIFO threshold level Table 600. RXFTLR Register Bits Name Description Type Reset 31:8 Reserved.
RP2040 Datasheet Description Status register Table 603. SR Register Bits Name Description Type Reset 31:7 Reserved. - - - 6 DCOL Data collision error RO 0x0 5 TXE Transmission error RO 0x0 4 RFF Receive FIFO full RO 0x0 3 RFNE Receive FIFO not empty RO 0x0 2 TFE Transmit FIFO empty RO 0x0 1 TFNF Transmit FIFO not full RO 0x0 0 BUSY SSI busy flag RO 0x0 SSI: IMR Register Offset: 0x2c Description Interrupt mask Table 604.
RP2040 Datasheet SSI: RISR Register Offset: 0x34 Description Raw interrupt status Table 606. RISR Register Bits Name Description Type Reset 31:6 Reserved.
RP2040 Datasheet Table 609. RXUICR Register Bits Description Type Reset 31:1 Reserved. - - 0 Clear-on-read receive FIFO underflow interrupt RO 0x0 SSI: MSTICR Register Offset: 0x44 Description Multi-master interrupt clear Table 610. MSTICR Register Bits Description Type Reset 31:1 Reserved. - - 0 Clear-on-read multi-master contention interrupt RO 0x0 SSI: ICR Register Offset: 0x48 Description Interrupt clear Table 611. ICR Register Bits Description Type Reset 31:1 Reserved.
RP2040 Datasheet Description DMA RX data level Table 614. DMARDLR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 DMARDL Receive data watermark level (DMARDLR+1) RW 0x00 SSI: IDR Register Offset: 0x58 Description Identification register Table 615. IDR Register Bits Name Description Type Reset 31:0 IDCODE Peripheral dentification code RO 0x51535049 Type Reset RO 0x3430312a SSI: SSI_VERSION_ID Register Offset: 0x5c Description Version ID Table 616.
RP2040 Datasheet Description SPI control Table 619. SPI_CTRLR0 Register Bits Name Description Type Reset 31:24 XIP_CMD SPI Command to send in XIP mode (INST_L = 8-bit) or to RW 0x03 append to Address (INST_L = 0-bit) 23:19 Reserved.
RP2040 Datasheet Chapter 5. Electrical and Mechanical Physical and electrical details of the RP2040 chip. 5.1. Package Figure 166. Top down view (left, top) and side view (right, top), along with bottom view (left, bottom) of the RP2040 QFN-56 package PIN 1 NOTE There is no standard size for the central GND pad (or ePad) with QFNs. However, the one on RP2040 is smaller than most. This means that standard 0.4mm QFN-56 footprints provided with CAD tools may need adjusting.
RP2040 Datasheet Figure 167. Recommended PCB 7.75 Footprint for the 6.00 RP2040 QFN-56 3.20 package 0.20 7.75 6.00 3.20 5.40 0.20 1.175 0.875 0.40 5.40 Dimensions in mm 5.1.2. Compliance RP2040 is compliant to Moisture Sensitivity Level 1. RP2040 is compliant to the requirement of REACH Substances of Very High Concern (SVHC) that ECHA announced on 25 June 2020.
RP2040 Datasheet Figure 168. RP2040 QFN-56 package pinout 5.2.2. Pin Definitions 5.2.2.1. Pin Types In the following GPIO Pin table (Table 622), the pin types are defined as shown below. Table 621. Pin Types Pin Type Direction Description Digital In Input only Standard Digital. Programmable Pull-Up, Pull-Down, Slew Rate, Digital IO Bi-directional Digital In (FT) Input only Schmitt Trigger and Drive Strength. Default Drive Strength is 4mA. Fault Tolerant Digital.
RP2040 Datasheet 5.2.2.2. Pin List Table 622.
RP2040 Datasheet Name Table 624. Crystal oscillator pins Number Type Power Domain QSPI_SD3 51 Digital IO IOVDD QSPI_SCLK 52 Digital IO IOVDD QSPI_SD0 53 Digital IO IOVDD QSPI data QSPI_SD2 54 Digital IO IOVDD QSPI data QSPI_SD1 55 Digital IO IOVDD QSPI data QSPI_CSn 56 Digital IO IOVDD Name Reset State QSPI data Pull-Down Pull-Up Number Type Power Domain 20 Analogue (XOSC) IOVDD XIN Description QSPI clock QSPI chip select Description Crystal oscillator.
RP2040 Datasheet 5.2.3. Pin Specifications The following electrical specifications are obtained from characterisation over the specified temperature and voltage ranges, as well as process variation, unless the specification is marked as 'Simulated'. In this case, the data is for information purposes only, and is not guaranteed. 5.2.3.1. Absolute Maximum Ratings Table 629.
RP2040 Datasheet Parameter Input Voltage Low Symbol Minimum Maximum Units VIL -0.3 0.7 V VIL -0.3 0.8 V VHYS 0.1 * IOVDD Comment @ IOVDD=2.5V Input Voltage Low @ IOVDD=3.3V Input Hysteresis V Voltage @ Schmitt Trigger enabled IOVDD=1.8V Input Hysteresis VHYS 0.2 V Voltage @ Schmitt Trigger enabled IOVDD=2.5V Input Hysteresis VHYS 0.2 V Voltage @ Schmitt Trigger enabled IOVDD=3.3V Output Voltage VOH 1.24 IOVDD V High @ IOVDD=1.8V Output Voltage on setting VOH 1.
RP2040 Datasheet Parameter Single Ended Input Symbol Minimum VIHSE 2 Maximum Units Comment V Voltage High Single Ended Input VILSE 0.8 V Voltage Low Differential Input VIHDIFF 0.2 V Voltage High Differential Input VILDIFF -0.2 V Voltage Low Output Voltage VOH 2.8 USB_VDD V VOL 0 0.3 V RPU2 0.873 1.548 kΩ RPU1&2 1.398 3.063 kΩ RPD 14.25 15.
RP2040 Datasheet the pin. The Output High Voltage (VOH) is defined as the lowest voltage the output pin can be when driven to a logic 1 with a particular selected drive strength; e.g., 4mA being sourced by the pin whilst in 4mA drive strength mode. The Output Low Voltage is similar, but with a logic 0 being driven. In addition to this, the sum of all the IO currents being sourced (i.e. when outputs are being driven high) from the IOVDD bank (essentially the GPIO and QSPI pins), must not exceed IIOVDD_MAX.
RP2040 Datasheet Power Supply USB_VDD Supplies Min Typ Max Units USB PHY 3.135 3.3 3.63 V ADC 1.62 3.3 3.63 V ADC_AVDDb a If IOVDD <2.5V, GPIO VOLTAGE_SELECT registers should be adjusted accordingly. See Section 2.9 for details. b ADC performance will be compromised at voltages below 2.97V 5.4.
RP2040 Datasheet Software Usecase Typical Max. Average Typical Max. Average Typical Max. Average Average DVDD DVDD current Average IOVDD current Average USB_VDD USB_VDD current Current IOVDD Current Units Current Sleep 0.39 4.5 - - - - mA 5.4.1.
RP2040 Datasheet Appendix A: Register Field Types Standard types RW The processor can write to this field and read the value back. RO The processor can only read this field. WO The processor can only write to this field. Clear types SC This is a single bit that is written to by the processor and then cleared on the next clock cycle. An example use of this would be a start bit that triggers an event, and then clears again so the event doesn’t keep triggering.
RP2040 Datasheet RWF Implementation defined read to, and write from the hardware.
RP2040 Datasheet Appendix B: Errata Hardware blocks are listed alphabetically. Errata are listed numerically under the relevant block. Bootrom RP2040-E9 Reference RP2040-E9 Summary ROM bootloader cannot boot directly into XIP cache-as-SRAM Description The XIP cache can be used as an additional 16 kB SRAM bank when XIP caching is disabled (Section 2.6.3.1). The UF2 bootloader supports RAM-only UF2 binaries, which it loads directly into memory, and enters via a watchdog reboot.
RP2040 Datasheet RP2040-E10 Reference RP2040-E10 Summary BADWRITE field in ROSC STATUS register is unreliable Description The BADWRITE field in the ROSC STATUS register was intended to report when invalid values had been written to other ROSC registers. However due to internal bugs the ROSC:STATUS BADWRITE field is unreliable. Workaround Do not use ROSC:STATUS BADWRITE field Affects RP2040B0, RP2040B1 Fixed by Not fixed, do not use. This field is not used by the C SDK.
RP2040 Datasheet RP2040-E2 Reference RP2040-E2 Summary USB device endpoint abort is not cleared. Description The USB device controller (Section 4.1) has the ability to abort any pending transactions on an endpoint by setting that endpoint’s bit in the EP_ABORT register. Due to a logic error, the USB device controller will reply with NAKs forever on all endpoints if a transaction is initiated for any endpoint with the EP_ABORT bit set. Workaround Do not use the EP_ABORT bits.
RP2040 Datasheet RP2040-E5 Reference RP2040-E5 Summary USB device fails to exit RESET state on busy USB bus. Description The USB bus RESET state is triggered by the host sending SE0 for 10ms to the device. The USB device controller requires 800μs of idle (J-state) after a bus reset before moving to the CONNECTED state. Without this idle time, the USB device does not connect and will not receive any packets from the host, and so does not enumerate.
RP2040 Datasheet Description The watchdog (Section 4.7) has a 24-bit counter, that decrements every tick, starting from a user defined value set in LOAD register. There is a logic error which means the counter is decremented twice per tick, instead of once per tick. In a recommended setup where the tick occurs at 1μs intervals, this halves the maximum time between resetting the watchdog counter from ~16.7 seconds to ~8.3 seconds. Workaround Use double the desired value in LOAD.
RP2040 Datasheet Appendix C: Documentation Release History Table 638. Documentation Release History Release Date 1.0 21/Jan/2021 • Initial release 1.1 26/Jan/2021 • Minor corrections • Extra information about using DMA with ADC • Clarified M0+ and SIO CPUID registers • Added more discussion of Timers • Update Windows and macOS build instructions • Renamed books and optimised size of output PDFs 1.
RP2040 Datasheet Release Date 1.4.1 13/Apr/2021 Description • Minor corrections • Clarified that all source code in the documentation is under the 3-Clause BSD license. 1.5 07/Jun/2021 • Minor updates and corrections • Updated FAQ • Added SDK release history • To accompany the V1.2.0 release of the C SDK 1.6 23/Jun/2021 • Minor updates and corrections • ADC information updated • Added errata E11 The latest release can be found at https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf.
