Datasheet

Ê16 // These buffers will be DMA'd to the UART, one after the other.
Ê17
Ê18 const char word0[] = "Transferring ";
Ê19 const char word1[] = "one ";
Ê20 const char word2[] = "word ";
Ê21 const char word3[] = "at ";
Ê22 const char word4[] = "a ";
Ê23 const char word5[] = "time.\n";
Ê24
Ê25 // Note the order of the fields here: it's important that the length is before
Ê26 // the read address, because the control channel is going to write to the last
Ê27 // two registers in alias 3 on the data channel:
Ê28 // +0x0 +0x4 +0x8 +0xC (Trigger)
Ê29 // Alias 0: READ_ADDR WRITE_ADDR TRANS_COUNT CTRL
Ê30 // Alias 1: CTRL READ_ADDR WRITE_ADDR TRANS_COUNT
Ê31 // Alias 2: CTRL TRANS_COUNT READ_ADDR WRITE_ADDR
Ê32 // Alias 3: CTRL WRITE_ADDR TRANS_COUNT READ_ADDR
Ê33 //
Ê34 // This will program the transfer count and read address of the data channel,
Ê35 // and trigger it. Once the data channel completes, it will restart the
Ê36 // control channel (via CHAIN_TO) to load the next two words into its control
Ê37 // registers.
Ê38
Ê39 const struct {uint32_t len; const char *data;} control_blocks[] = {
Ê40 {count_of(word0) - 1, word0}, // Skip null terminator
Ê41 {count_of(word1) - 1, word1},
Ê42 {count_of(word2) - 1, word2},
Ê43 {count_of(word3) - 1, word3},
Ê44 {count_of(word4) - 1, word4},
Ê45 {count_of(word5) - 1, word5},
Ê46 {0, NULL} // Null trigger to end chain.
Ê47 };
Ê48
Ê49 int main() {
Ê50 #ifndef uart_default
Ê51 #warning dma/control_blocks example requires a UART
Ê52 #else
Ê53 stdio_init_all();
Ê54 puts("DMA control block example:");
Ê55
Ê56 // ctrl_chan loads control blocks into data_chan, which executes them.
Ê57 int ctrl_chan = dma_claim_unused_channel(true);
Ê58 int data_chan = dma_claim_unused_channel(true);
Ê59
Ê60 // The control channel transfers two words into the data channel's control
Ê61 // registers, then halts. The write address wraps on a two-word
Ê62 // (eight-byte) boundary, so that the control channel writes the same two
Ê63 // registers when it is next triggered.
Ê64
Ê65 dma_channel_config c = dma_channel_get_default_config(ctrl_chan);
Ê66 channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
Ê67 channel_config_set_read_increment(&c, true);
Ê68 channel_config_set_write_increment(&c, true);
Ê69 channel_config_set_ring(&c, true, 3); // 1 << 3 byte boundary on write ptr
Ê70
Ê71 dma_channel_configure(
Ê72 ctrl_chan,
Ê73 &c,
Ê74 &dma_hw->ch[data_chan].al3_transfer_count, // Initial write address
Ê75 &control_blocks[0], // Initial read address
Ê76 2, // Halt after each control block
Ê77 false // Don't start yet
Ê78 );
RP2040 Datasheet
2.5. DMA 101