Datasheet

Ê79
Ê80 // The data channel is set up to write to the UART FIFO (paced by the
Ê81 // UART's TX data request signal) and then chain to the control channel
Ê82 // once it completes. The control channel programs a new read address and
Ê83 // data length, and retriggers the data channel.
Ê84
Ê85 c = dma_channel_get_default_config(data_chan);
Ê86 channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
Ê87 channel_config_set_dreq(&c, DREQ_UART0_TX + 2 * uart_get_index(uart_default));
Ê88 // Trigger ctrl_chan when data_chan completes
Ê89 channel_config_set_chain_to(&c, ctrl_chan);
Ê90 // Raise the IRQ flag when 0 is written to a trigger register (end of chain):
Ê91 channel_config_set_irq_quiet(&c, true);
Ê92
Ê93 dma_channel_configure(
Ê94 data_chan,
Ê95 &c,
Ê96 &uart_get_hw(uart_default)->dr,
Ê97 NULL, // Initial read address and transfer count are unimportant;
Ê98 0, // the control channel will reprogram them each time.
Ê99 false // Don't start yet.
100 );
101
102 // Everything is ready to go. Tell the control channel to load the first
103 // control block. Everything is automatic from here.
104 dma_start_channel_mask(1u << ctrl_chan);
105
106 // The data channel will assert its IRQ flag when it gets a null trigger,
107 // indicating the end of the control block list. We're just going to wait
108 // for the IRQ flag instead of setting up an interrupt handler.
109 while (!(dma_hw->intr & 1u << data_chan))
110 tight_loop_contents();
111 dma_hw->ints0 = 1u << data_chan;
112
113 puts("DMA finished.");
114 #endif
115 }
2.5.7. List of Registers
The DMA registers start at a base address of 0x50000000 (defined as DMA_BASE in SDK).
Table 120. List of
DMA registers
Offset Name Info
0x000 CH0_READ_ADDR DMA Channel 0 Read Address pointer
0x004 CH0_WRITE_ADDR DMA Channel 0 Write Address pointer
0x008 CH0_TRANS_COUNT DMA Channel 0 Transfer Count
0x00c CH0_CTRL_TRIG DMA Channel 0 Control and Status
0x010 CH0_AL1_CTRL Alias for channel 0 CTRL register
0x014 CH0_AL1_READ_ADDR Alias for channel 0 READ_ADDR register
0x018 CH0_AL1_WRITE_ADDR Alias for channel 0 WRITE_ADDR register
0x01c CH0_AL1_TRANS_COUNT_TRIG Alias for channel 0 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
RP2040 Datasheet
2.5. DMA 102