Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Description
DMA Channel N Read Address pointer
Table 121.
CH0_READ_ADDR,
CH1_READ_ADDR, …,
CH10_READ_ADDR,
CH11_READ_ADDR
Registers
Bits Description Type Reset
31:0 This register updates automatically each time a read completes. The current
value is the next address to be read by this channel.
RW 0x00000000
DMA: CH0_WRITE_ADDR, CH1_WRITE_ADDR, …, CH10_WRITE_ADDR,
CH11_WRITE_ADDR Registers
Offsets: 0x004, 0x044, …, 0x284, 0x2c4
Description
DMA Channel N Write Address pointer
Table 122.
CH0_WRITE_ADDR,
CH1_WRITE_ADDR, …,
CH10_WRITE_ADDR,
CH11_WRITE_ADDR
Registers
Bits Description Type Reset
31:0 This register updates automatically each time a write completes. The current
value is the next address to be written by this channel.
RW 0x00000000
DMA: CH0_TRANS_COUNT, CH1_TRANS_COUNT, …, CH10_TRANS_COUNT,
CH11_TRANS_COUNT Registers
Offsets: 0x008, 0x048, …, 0x288, 0x2c8
Description
DMA Channel N Transfer Count
Table 123.
CH0_TRANS_COUNT,
CH1_TRANS_COUNT,
…,
CH10_TRANS_COUNT,
CH11_TRANS_COUNT
Registers
Bits Description Type Reset
31:0 Program the number of bus transfers a channel will perform before halting.
Note that, if transfers are larger than one byte in size, this is not equal to the
number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of
transfers remaining, updating automatically each time a write transfer
completes.
Writing this register sets the RELOAD value for the transfer counter. Each time
this channel is triggered, the RELOAD value is copied into the live transfer
counter. The channel can be started multiple times, and will perform the same
number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is
used as a trigger, the written value is used immediately as the length of the
new transfer sequence, as well as being written to RELOAD.
RW 0x00000000
DMA: CH0_CTRL_TRIG Registers
Offsets: 0x00c
Description
DMA Channel N Control and Status
Table 124.
CH0_CTRL_TRIG
Registers
RP2040 Datasheet
2.5. DMA 112