Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 128.
CH0_AL1_TRANS_COU
NT_TRIG,
CH1_AL1_TRANS_COU
NT_TRIG, …,
CH10_AL1_TRANS_CO
UNT_TRIG,
CH11_AL1_TRANS_CO
UNT_TRIG Registers
Bits Description Type Reset
31:0 Alias for channel N TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
RO -
DMA: CH0_AL2_CTRL, CH1_AL2_CTRL, …, CH10_AL2_CTRL, CH11_AL2_CTRL
Registers
Offsets: 0x020, 0x060, …, 0x2a0, 0x2e0
Table 129.
CH0_AL2_CTRL,
CH1_AL2_CTRL, …,
CH10_AL2_CTRL,
CH11_AL2_CTRL
Registers
Bits Description Type Reset
31:0 Alias for channel N CTRL register RO -
DMA: CH0_AL2_TRANS_COUNT, CH1_AL2_TRANS_COUNT, …,
CH10_AL2_TRANS_COUNT, CH11_AL2_TRANS_COUNT Registers
Offsets: 0x024, 0x064, …, 0x2a4, 0x2e4
Table 130.
CH0_AL2_TRANS_COU
NT,
CH1_AL2_TRANS_COU
NT, …,
CH10_AL2_TRANS_CO
UNT,
CH11_AL2_TRANS_CO
UNT Registers
Bits Description Type Reset
31:0 Alias for channel N TRANS_COUNT register RO -
DMA: CH0_AL2_READ_ADDR, CH1_AL2_READ_ADDR, …,
CH10_AL2_READ_ADDR, CH11_AL2_READ_ADDR Registers
Offsets: 0x028, 0x068, …, 0x2a8, 0x2e8
Table 131.
CH0_AL2_READ_ADDR
,
CH1_AL2_READ_ADDR
, …,
CH10_AL2_READ_ADD
R,
CH11_AL2_READ_ADD
R Registers
Bits Description Type Reset
31:0 Alias for channel N READ_ADDR register RO -
DMA: CH0_AL2_WRITE_ADDR_TRIG, CH1_AL2_WRITE_ADDR_TRIG, …,
CH10_AL2_WRITE_ADDR_TRIG, CH11_AL2_WRITE_ADDR_TRIG Registers
Offsets: 0x02c, 0x06c, …, 0x2ac, 0x2ec
Table 132.
CH0_AL2_WRITE_ADD
R_TRIG,
CH1_AL2_WRITE_ADD
R_TRIG, …,
CH10_AL2_WRITE_AD
DR_TRIG,
CH11_AL2_WRITE_AD
DR_TRIG Registers
Bits Description Type Reset
31:0 Alias for channel N WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
RO -
DMA: CH0_AL3_CTRL, CH1_AL3_CTRL, …, CH10_AL3_CTRL, CH11_AL3_CTRL
Registers
Offsets: 0x030, 0x070, …, 0x2b0, 0x2f0
Table 133.
CH0_AL3_CTRL,
CH1_AL3_CTRL, …,
CH10_AL3_CTRL,
CH11_AL3_CTRL
Registers
Bits Description Type Reset
31:0 Alias for channel N CTRL register RO -
DMA: CH0_AL3_WRITE_ADDR, CH1_AL3_WRITE_ADDR, …,
CH10_AL3_WRITE_ADDR, CH11_AL3_WRITE_ADDR Registers
Offsets: 0x034, 0x074, …, 0x2b4, 0x2f4
RP2040 Datasheet
2.5. DMA 116