Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 134.
CH0_AL3_WRITE_ADD
R,
CH1_AL3_WRITE_ADD
R, …,
CH10_AL3_WRITE_AD
DR,
CH11_AL3_WRITE_AD
DR Registers
Bits Description Type Reset
31:0 Alias for channel N WRITE_ADDR register RO -
DMA: CH0_AL3_TRANS_COUNT, CH1_AL3_TRANS_COUNT, …,
CH10_AL3_TRANS_COUNT, CH11_AL3_TRANS_COUNT Registers
Offsets: 0x038, 0x078, …, 0x2b8, 0x2f8
Table 135.
CH0_AL3_TRANS_COU
NT,
CH1_AL3_TRANS_COU
NT, …,
CH10_AL3_TRANS_CO
UNT,
CH11_AL3_TRANS_CO
UNT Registers
Bits Description Type Reset
31:0 Alias for channel N TRANS_COUNT register RO -
DMA: CH0_AL3_READ_ADDR_TRIG, CH1_AL3_READ_ADDR_TRIG, …,
CH10_AL3_READ_ADDR_TRIG, CH11_AL3_READ_ADDR_TRIG Registers
Offsets: 0x03c, 0x07c, …, 0x2bc, 0x2fc
Table 136.
CH0_AL3_READ_ADDR
_TRIG,
CH1_AL3_READ_ADDR
_TRIG, …,
CH10_AL3_READ_ADD
R_TRIG,
CH11_AL3_READ_ADD
R_TRIG Registers
Bits Description Type Reset
31:0 Alias for channel N READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
RO -
DMA: CH1_CTRL_TRIG Register
Offset: 0x04c
Description
DMA Channel 1 Control and Status
Table 137.
CH1_CTRL_TRIG
Register
Bits Name Description Type Reset
31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags.
The channel halts when it encounters any bus error, and
always raises its channel IRQ flag.
RO 0x0
30 READ_ERROR If 1, the channel received a read bus error. Write one to
clear.
READ_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 3 transfers later)
WC 0x0
29 WRITE_ERROR If 1, the channel received a write bus error. Write one to
clear.
WRITE_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 5 transfers later)
WC 0x0
28:25 Reserved. - - -
24 BUSY This flag goes high when the channel starts a new transfer
sequence, and low when the last transfer of that sequence
completes. Clearing EN while BUSY is high pauses the
channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag),
see CHAN_ABORT.
RO 0x0
RP2040 Datasheet
2.5. DMA 117