Datasheet

Bits Name Description Type Reset
23 SNIFF_EN If 1, this channel’s data transfers are visible to the sniff
hardware, and each transfer will advance the state of the
checksum. This only applies if the sniff hardware is
enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-
control- block basis.
RW 0x0
22 BSWAP Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the
two bytes of each halfword are swapped. For word data,
the four bytes of each word are swapped to reverse order.
RW 0x0
21 IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the
end of every transfer block. Instead, an IRQ is raised when
NULL is written to a trigger register, indicating the end of a
control block chain.
This reduces the number of interrupts to be serviced by
the CPU when transferring a DMA chain of many small
control blocks.
RW 0x0
20:15 TREQ_SEL Select a Transfer Request signal.
The channel uses the transfer request signal to pace its
data transfer rate. Sources for TREQ signals are internal
(TIMERS) or external (DREQ, a Data Request from the
system).
0x0 to 0x3a → select DREQ n as TREQ
0x3b → Select Timer 0 as TREQ
0x3c → Select Timer 1 as TREQ
0x3d → Select Timer 2 as TREQ (Optional)
0x3e → Select Timer 3 as TREQ (Optional)
0x3f → Permanent request, for unpaced transfers.
RW 0x00
14:11 CHAIN_TO When this channel completes, it will trigger the channel
indicated by CHAIN_TO. Disable by setting CHAIN_TO =
(this channel).
Reset value is equal to channel number (1).
RW 0x1
10 RING_SEL Select whether RING_SIZE applies to read or write
addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE)
boundary. If 1, write addresses are wrapped.
RW 0x0
9:6 RING_SIZE Size of address wrap region. If 0, don’t wrap. For values n
> 0, only the lower n bits of the address will change. This
wraps the address on a (1 << n) byte boundary, facilitating
access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This
can apply to either read or write addresses, based on
value of RING_SEL.
0x0 → RING_NONE
RW 0x0
RP2040 Datasheet
2.5. DMA 118