Datasheet

Bits Name Description Type Reset
5 INCR_WRITE If 1, the write address increments with each transfer. If 0,
each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral
transfers.
RW 0x0
4 INCR_READ If 1, the read address increments with each transfer. If 0,
each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory
transfers.
RW 0x0
3:2 DATA_SIZE Set the size of each bus transfer (byte/halfword/word).
READ_ADDR and WRITE_ADDR advance by this amount
(1/2/4 bytes) with each transfer.
0x0 → SIZE_BYTE
0x1 → SIZE_HALFWORD
0x2 → SIZE_WORD
RW 0x0
1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in
issue scheduling: in each scheduling round, all high
priority channels are considered first, and then only a
single low priority channel, before returning to the high
priority channels.
This only affects the order in which the DMA schedules
channels. The DMA’s bus priority is not changed. If the
DMA is not saturated then a low priority channel will see
no loss of throughput.
RW 0x0
0 EN DMA Channel Enable.
When 1, the channel will respond to triggering events,
which will cause it to become BUSY and start transferring
data. When 0, the channel will ignore triggers, stop issuing
transfers, and pause the current transfer sequence (i.e.
BUSY will remain high if already high)
RW 0x0
DMA: CH5_CTRL_TRIG Register
Offset: 0x14c
Description
DMA Channel 5 Control and Status
Table 141.
CH5_CTRL_TRIG
Register
Bits Name Description Type Reset
31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags.
The channel halts when it encounters any bus error, and
always raises its channel IRQ flag.
RO 0x0
30 READ_ERROR If 1, the channel received a read bus error. Write one to
clear.
READ_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 3 transfers later)
WC 0x0
RP2040 Datasheet
2.5. DMA 126