Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
29 WRITE_ERROR If 1, the channel received a write bus error. Write one to
clear.
WRITE_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 5 transfers later)
WC 0x0
28:25 Reserved. - - -
24 BUSY This flag goes high when the channel starts a new transfer
sequence, and low when the last transfer of that sequence
completes. Clearing EN while BUSY is high pauses the
channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag),
see CHAN_ABORT.
RO 0x0
23 SNIFF_EN If 1, this channel’s data transfers are visible to the sniff
hardware, and each transfer will advance the state of the
checksum. This only applies if the sniff hardware is
enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-
control- block basis.
RW 0x0
22 BSWAP Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the
two bytes of each halfword are swapped. For word data,
the four bytes of each word are swapped to reverse order.
RW 0x0
21 IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the
end of every transfer block. Instead, an IRQ is raised when
NULL is written to a trigger register, indicating the end of a
control block chain.
This reduces the number of interrupts to be serviced by
the CPU when transferring a DMA chain of many small
control blocks.
RW 0x0
20:15 TREQ_SEL Select a Transfer Request signal.
The channel uses the transfer request signal to pace its
data transfer rate. Sources for TREQ signals are internal
(TIMERS) or external (DREQ, a Data Request from the
system).
0x0 to 0x3a → select DREQ n as TREQ
0x3b → Select Timer 0 as TREQ
0x3c → Select Timer 1 as TREQ
0x3d → Select Timer 2 as TREQ (Optional)
0x3e → Select Timer 3 as TREQ (Optional)
0x3f → Permanent request, for unpaced transfers.
RW 0x00
14:11 CHAIN_TO When this channel completes, it will trigger the channel
indicated by CHAIN_TO. Disable by setting CHAIN_TO =
(this channel).
Reset value is equal to channel number (5).
RW 0x5
RP2040 Datasheet
2.5. DMA 127