Datasheet

Bits Name Description Type Reset
1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in
issue scheduling: in each scheduling round, all high
priority channels are considered first, and then only a
single low priority channel, before returning to the high
priority channels.
This only affects the order in which the DMA schedules
channels. The DMA’s bus priority is not changed. If the
DMA is not saturated then a low priority channel will see
no loss of throughput.
RW 0x0
0 EN DMA Channel Enable.
When 1, the channel will respond to triggering events,
which will cause it to become BUSY and start transferring
data. When 0, the channel will ignore triggers, stop issuing
transfers, and pause the current transfer sequence (i.e.
BUSY will remain high if already high)
RW 0x0
DMA: CH10_CTRL_TRIG Register
Offset: 0x28c
Description
DMA Channel 10 Control and Status
Table 146.
CH10_CTRL_TRIG
Register
Bits Name Description Type Reset
31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags.
The channel halts when it encounters any bus error, and
always raises its channel IRQ flag.
RO 0x0
30 READ_ERROR If 1, the channel received a read bus error. Write one to
clear.
READ_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 3 transfers later)
WC 0x0
29 WRITE_ERROR If 1, the channel received a write bus error. Write one to
clear.
WRITE_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 5 transfers later)
WC 0x0
28:25 Reserved. - - -
24 BUSY This flag goes high when the channel starts a new transfer
sequence, and low when the last transfer of that sequence
completes. Clearing EN while BUSY is high pauses the
channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag),
see CHAN_ABORT.
RO 0x0
RP2040 Datasheet
2.5. DMA 138