Datasheet

Table 155. TIMER0,
TIMER1, TIMER2,
TIMER3 Registers
Bits Name Description Type Reset
31:16 X Pacing Timer Dividend. Specifies the X value for the (X/Y)
fractional timer.
RW 0x0000
15:0 Y Pacing Timer Divisor. Specifies the Y value for the (X/Y)
fractional timer.
RW 0x0000
DMA: MULTI_CHAN_TRIGGER Register
Offset: 0x430
Description
Trigger one or more channels simultaneously
Table 156.
MULTI_CHAN_TRIGGE
R Register
Bits Description Type Reset
31:16 Reserved. - -
15:0 Each bit in this register corresponds to a DMA channel. Writing a 1 to the
relevant bit is the same as writing to that channel’s trigger register; the
channel will start if it is currently enabled and not already busy.
SC 0x0000
DMA: SNIFF_CTRL Register
Offset: 0x434
Description
Sniffer Control
Table 157.
SNIFF_CTRL Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11 OUT_INV If set, the result appears inverted (bitwise complement)
when read. This does not affect the way the checksum is
calculated; the result is transformed on-the-fly between
the result register and the bus.
RW 0x0
10 OUT_REV If set, the result appears bit-reversed when read. This does
not affect the way the checksum is calculated; the result
is transformed on-the-fly between the result register and
the bus.
RW 0x0
9 BSWAP Locally perform a byte reverse on the sniffed data, before
feeding into checksum.
Note that the sniff hardware is downstream of the DMA
channel byteswap performed in the read master: if
channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both
enabled, their effects cancel from the sniffer’s point of
view.
RW 0x0
RP2040 Datasheet
2.5. DMA 145