Datasheet

Bits Name Description Type Reset
8:5 CALC
0x0 → Calculate a CRC-32 (IEEE802.3 polynomial)
0x1 → Calculate a CRC-32 (IEEE802.3 polynomial) with bit
reversed data
0x2 → Calculate a CRC-16-CCITT
0x3 → Calculate a CRC-16-CCITT with bit reversed data
0xe → XOR reduction over all data. == 1 if the total 1
population count is odd.
0xf → Calculate a simple 32-bit checksum (addition with a
32 bit accumulator)
RW 0x0
4:1 DMACH DMA channel for Sniffer to observe RW 0x0
0 EN Enable sniffer RW 0x0
DMA: SNIFF_DATA Register
Offset: 0x438
Description
Data accumulator for sniff hardware
Table 158.
SNIFF_DATA Register
Bits Description Type Reset
31:0 Write an initial seed value here before starting a DMA transfer on the channel
indicated by SNIFF_CTRL_DMACH. The hardware will update this register each
time it observes a read from the indicated channel. Once the channel
completes, the final result can be read from this register.
RW 0x00000000
DMA: FIFO_LEVELS Register
Offset: 0x440
Description
Debug RAF, WAF, TDF levels
Table 159.
FIFO_LEVELS Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:16 RAF_LVL Current Read-Address-FIFO fill level RO 0x00
15:8 WAF_LVL Current Write-Address-FIFO fill level RO 0x00
7:0 TDF_LVL Current Transfer-Data-FIFO fill level RO 0x00
DMA: CHAN_ABORT Register
Offset: 0x444
Description
Abort an in-progress transfer sequence on one or more channels
RP2040 Datasheet
2.5. DMA 146