Datasheet

Table 160.
CHAN_ABORT
Register
Bits Description Type Reset
31:16 Reserved. - -
15:0 Each bit corresponds to a channel. Writing a 1 aborts whatever transfer
sequence is in progress on that channel. The bit will remain high until any in-
flight transfers have been flushed through the address and data FIFOs.
After writing, this register must be polled until it returns all-zero. Until this
point, it is unsafe to restart the channel.
SC 0x0000
DMA: N_CHANNELS Register
Offset: 0x448
Table 161.
N_CHANNELS Register
Bits Description Type Reset
31:5 Reserved. - -
4:0 The number of channels this DMA instance is equipped with. This DMA
supports up to 16 hardware channels, but can be configured with as few as
one, to minimise silicon area.
RO -
DMA: CH0_DBG_CTDREQ, CH1_DBG_CTDREQ, …, CH10_DBG_CTDREQ,
CH11_DBG_CTDREQ Registers
Offsets: 0x800, 0x840, …, 0xa80, 0xac0
Table 162.
CH0_DBG_CTDREQ,
CH1_DBG_CTDREQ, …,
CH10_DBG_CTDREQ,
CH11_DBG_CTDREQ
Registers
Bits Description Type Reset
31:6 Reserved. - -
5:0 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it
can perform on the peripheral without overflow/underflow. Write any value:
clears the counter, and cause channel to re-initiate DREQ handshake.
RO 0x00
DMA: CH0_DBG_TCR, CH1_DBG_TCR, …, CH10_DBG_TCR, CH11_DBG_TCR
Registers
Offsets: 0x804, 0x844, …, 0xa84, 0xac4
Table 163.
CH0_DBG_TCR,
CH1_DBG_TCR, …,
CH10_DBG_TCR,
CH11_DBG_TCR
Registers
Bits Description Type Reset
31:0 Read to get channel TRANS_COUNT reload value, i.e. the length of the next
transfer
RO 0x00000000
2.6. Memory
RP2040 has embedded ROM and SRAM, and access to external Flash via a QSPI interface. Details of internal memory
are given below.
2.6.1. ROM
A 16kB read-only memory (ROM) is at address 0x00000000. The ROM contents are fixed at the time the silicon is
manufactured. It contains:
•
Initial startup routine
RP2040 Datasheet
2.6. Memory 147